In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

Grass, Eckhard

Jagdhold, Ulrich

Krstic, Milos

Maharatna, Koushik

Troya, Alfonso

Facta Universitatis Series : Electronics and Energetics

English

Southampton (e-Prints Soton)

FACTA UNIVERSITATIS (NI S)SER.: ELEC. ENERG. vol. 17, August 2004, 231-239Baseband Processor for IEEE 802.11a Standard withEmbedded BISTThis paper is dedicated to dear friend of my familly Prof. K. Tr¨ ondle on the occasionof his retirementMilo s Krsti´ c, Koushik Maharatna, Alfonso Troya,Eckhard Grass, and Ulrich JagdholdAbstract: In this paper results of an IEEE 802.11a compliant low-power basebandprocessor implementation are presented. The detailed structure of the baseband pro-cessor and its constituent blocks is given. A design for testability strategy based onBuilt-In Self-Test (BIST) is proposed. Finally, implementational results and powerestimation are reported.Keywords: IEEE 802.11a, Baseband processor, Low power, BIST.1 IntroductionFourth generation (4G) wireless and mobile systems are today very attractive forresearch and development. New types of services will be universally available toconsumers and for industrial applications with the use of 4G devices. Broadbandwireless networks will enable packet based high-speed data transfer suitable forvideo transmission and mobile Internet applications.This paper is based on the outcomes of a project that aims to develop a wirelessbroadband communication system in the 5 GHz band, compliant with the IEEE802.11a standard [1]. This standard species broadband communication systemsusing OFDM (Orthogonal Frequency Division Multiplexing) with data rates rang-ing from 6 - 54 Mbit/s. According to the standard, physical layer computationalManuscript received March 8, 2004.M. Krsti´ c, A. Troya, E. Grass and U. Jagdhold are with IHP Microelectronics, Im Tech-nologiepark 25, 15236 Frankfurt (Oder), Germany (e-mail: [krstic, troya, grass,jagdhold]@ihp-microelectronics.com). K. Maharatna is with University of Bristol (e-mail: Koushik.Maharatna@bristol.ac.uk).231232 M. Krsti´ c, K. Maharatna, A. Troya, E. Grass, and U. Jagdhold:requirements can be achieved by adequate digital baseband processing. A practicalimplementation of the IEEE 802.11a compliant baseband processor can be done inseveral ways. In general, software based baseband processing can be done usingeither a multiprocessor system or a single DSP processor with a number of hard-ware accelerators. The standard denes very intensive computational activities, andpossible software solutions lead to increased power dissipation.Therefore, we have decided to use a dedicated ASIC (Application Specic In-tegrated Circuit) for baseband processing. The processing algorithm dened by thestandard corresponds to a datapath architecture of transmitter and receiver. To de-centralize some timing critical control functions atoken-ow approach wasadopted[2]. Every block in the baseband processor has an input signal, which indicates thatvalid data is ready for processing. A similar signal is generated by every blockupon output, to indicate that the subsequent block can process data. The token-ow approach can easily be expanded with clock gating. In this way an efcientpower saving mechanism is implemented.In the following sections, rst the architecture of the processor will be de-scribed. Then power saving mechanism of the baseband processor will be dis-cussed, as well as the testing strategy. Finally, implementational results and someconclusions will be presented.2 Architecture of the Baseband ProcessorA block diagram of the Baseband processor is shown in Fig. 1. In order to achievelow power dissipation and to optimize silicon usage, the architecture is dividedin two principle blocks: Transmitter and Receiver. According to this division,the baseband processing can provide two almost independent dataow directions:transmit and receive.The transmitter block consists of an input buffer, scrambler, signal eld gener-ator, encoder, interleaver, mapper, 64-point IFFT/FFT (Inverse Fast Fourier Trans-form / Fast Fourier Transform) and circuitry for pilot insertion (with pilot scram-bler), guard interval insertion, and preamble insertion. The IFFT/FFT is a singleblock used in both, receive and transmit direction in order to optimize the basebandprocessor structure. On the other hand, this solution is more complex for imple-mentation, because of incomplete decoupling between the transmitter and receiverdatapath.The standard [1] denes the procedure for the receiver and transmitter datapathprocessing. A fundamental issue, not tackled by the standard, is the mechanismof the synchronization and the channel estimation. The solution for this problemis one of the most important outcomes of our work. The synchronizer has to ful-Baseband Processor for IEEE 802.11a Standard with Embedded BIST 233Fig. 1. Block diagram of the Baseband processor with embedded BIST.ll the following operations: frame detection, carrier frequency offset estimation,symbol timing estimation, extraction of the reference channel and data reordering.A block scheme of the synchronizer is given in Fig. 3. In order to obtain a powerefcient design, the synchronizer structure was split into two mutually exclusivepaths: tracking data path and processing data path [3]. The main function of thetracking data path is to detect an incoming frame by searching for the periodicstructure of the preamble symbols and to estimate the carrier frequency offset. In234 M. Krsti´ c, K. Maharatna, A. Troya, E. Grass, and U. Jagdhold:Fig. 2. Block diagram of the proposed Channel Estimator.our design, a wide range of frequency offsets can be estimated (￿80 ppm) usingonly two autocorrelators. The output of one of those is also used in the frame de-tection mechanism. This provides a signicant core area reduction in comparisonwith other proposed solutions, as in [4]. Here, the range of estimated frequencyoffsets is￿40 ppm and three autocorrelators are used for the frame detection, butonly two of them for the frequency offset estimation. In our design, frame detectionis performed by a plateau detector, which has to detect a specic plateau shape inthe incoming preamble symbols. The activity of the processing datapath starts afterthe frame is detected and the estimated value for frequency offset is available.This part of the synchronizer performs the carrier frequency error correction,estimates the symbol timing and obtains the reference channel estimation. It con-sists of an NCO(Numerically Controlled Oscillator, in this case a CORDICproces-sor operating in rotational mode), FFT processor and a simplied crosscorrelatorbased on XNOR gates [3].Channel estimation is based on a decision-directed method [5] with simpliedresidual phase estimation and correction mechanism. This type of channel esti-mation is based on a feedback loop. Therefore our receiver involves additionalencoding, interleaving and mapping (Fig. 2). The interesting point in this conceptis that it makes use of a division unit to correct the data samples (equalizer). Theestimator is designed in such a way that the samples of symbol i are used to calcu-late an estimation of the channel, which will be used to correct the symbol i￿ D,where D is the delay introduced by the feedback loop.Other blocks on the receiving path, mainly dened by the standard, are demap-Baseband Processor for IEEE 802.11a Standard with Embedded BIST 235Fig. 3. General scheme of the Synchronizer.per, deinterleaver, descrambler, Viterbi decoder, and additional buffers.In order to simplify processing of the data and optimize power consumptionto the maximal extent, the complete structure was divided into two clock domains.Computationally complex blocks without high data throughput requirements weredesigned for 20 MHz and high data throughput demanding circuits were designedfor 80 MHz.3 Power Saving Issues in the Baseband ProcessorIn order to avoid unnecessary waste of energy, clock gating is introduced as a powersaving technique in the baseband processor. This circuit is divided into the trans-mitter (Tx) and the receiver (Rx) section, and accordingly, for the power saving pur-pose, blocks from Tx and Rx will not be in the same clock domain. The FFT/IFFTblock is used both in the receiver and transmitter and it is dened as an indepen-dent clock domain. This block will be triggered whenever the transmitter is active.Additionally, this block will be used in the receiving phase when coarse synchro-nization is reached and data should be processed in the FFT. Our transmitter con-sists of two clock domains: one that assembles 80 MHz blocks and other for 20MHz blocks. Clocks for this both blocks will be enabled only when the basebandprocessor is in transmit mode. In the receiver, the tracking synchronizer block is astand-alone domain. This block will be active most of the processing time, becausethe baseband processor is always in receive mode, except for the time when it trans-mits. Also, in receive mode for most of the time the baseband processor will searchfor coarse synchronization. With this domain separation we can save a signicantamount of energy. Other domains in the receiver are 20 MHz domains for synchro-nizer and channel estimator and 80 MHz domain for blocks as Viterbi decoder anddeinterleaver. Those blocks will be activated only when coarse synchronization is236 M. Krsti´ c, K. Maharatna, A. Troya, E. Grass, and U. Jagdhold:reached and there is data to be processed. After processing all data from one frame,the processing domains will be deactivated and the tracking synchronizer will againstart toggling.4 Baseband chip design for testabilityThe baseband processor has very complex datapath architecture. In order to guar-antee reliable operation it is necessary to provide a certain level of testability. Astandard procedure in the synchronous world is to apply scan- based testing. In thecase of the baseband processor we have decided not to use that approach. Scan test-ing could decrease performances of our system, and requires expensive hardwaretesters. Additionally, for datapath architectures Built-in Self-Test (BIST) could bedesigned in such way, that it tests most of the system functionality with very lowcost in additional hardware and decreased performance.It would be ideal if we could just in one run, perform testing of the completebaseband processor. Unfortunately, this baseband processor implementation doesnot allow that. The critical part is FFT/IFFT, which is a single block and can beeither in transmit or receive mode and not both in the same time. All other parts inreceiving and transmitting datapath are completely decoupled.For that reason, we decided to create two separate BIST paths (domains). Oneis for testing the receiver and the other for testing the transmitter. In both caseswe have designed Test Pattern Generators (TPG). Generally, a TPG consists of aLinear Feedback Shift Register (LFSR). In the receiver direction, to activate deeperpipeline stages, it was necessary to add to the TPG also a preamble and signal eldgenerator. Otherwise our testing sequence would never go out from the synchro-nizer. In the transmitter stage TPG also has to include a starting sequence thatenables transmission of data. In both BISTs, four Test Data Extractors (TDE) areimplemented. A TDE is essentially also a LFSR. The idea behind that is to havemore information about the results of testing. Generally, validity of the test is sig-naled with the TDEs at the output stages of transmitter and receiver. Additionallyat three positions inside the transmitter and receiver datapath, additional TDEs areconnected. They could provide information about some errors that could be maskedin the following dataow. Additionally, when the nal TDE gives an erroneous re-sult, we could isolate the errors and nd erroneous blocks inside the receiver andtransmitter. Only one-bit information is used for BIST test result collection. Whenthe test is nished, pulses at the Bist ok line should indicate validity of the internaltest and the level of the nal value will indicate correctness of the output data.Baseband Processor for IEEE 802.11a Standard with Embedded BIST 2375 ImplementationThe complete baseband processor was modeled in VHDL and synthesized usingour in-house 0.25 mm standard cell library. It`s drawing cell area, including allblocks from Fig. 1, is 32,85 mm2 (equivalent transistor count is around 1 Mil-lion). In Table 1 some synthesis results for our technology are given, where Tx￿indicates transmitter components and Rx￿ stands for receiver components. FromTable 1 it can be noticed that the dominant hardware part is the receiver. It uses67.6% of the chip cell area. Generally, the most silicon consuming componentsare synchronizer, channel estimator, Viterbi decoder and FFT/IFFT. Based on theresult of the synthesis, the layout of the baseband chip is performed. According toafter-layout power estimation with Synopsys Prime Power [6], the expected powerconsumption is 393 mW for the scenario of a real transceiver application. Thisapplication consists of the reception of 43 bytes and subsequent transmission ofthe standard acknowledge of 14 bytes. From this point of view most of the poweris spent in the Viterbi processor (13.5%), FFT/IFFT (10.4%) and Transmitter ingeneral (13%). One could observe that the total power spent in receiver is around63.3 %. Remaining power is utilized by the clock tree, which impact is analyzedseparately.Table 1. Baseband processor synthesis resultsHardware part Cell area (mm2) Cell area (%) Power (mW) Power (%)Tx 3.064 9.3 63 16Interleaver 0.501 1.5 13 3.3Pilot insert 0.820 2.5 31 7.9Guard insert 1.011 3.1 4 1Inputbuffer 0.201 0.6 1 0.2Tx BIST 0.130 0.4 1 0.2Rx 22.201 67.6 145 36.9Synchronizer 6.183 18.8 25 6.4Chanel est. 5.297 16.1 15 3.8Viterbi dec 5.910 18.0 53 13.5CE buffer 1.446 4.4 13 3.3Deinterleaver 1.786 5.4 21 5.3Demapper 0.422 1.3 1 0.2Interleaver 0.630 1.9 7 1.8Rx BIST 0.247 0.8 1 0.2FFT/IFFT 7.556 32.0 41 10.4Total 32.851 100 393 100Die photo of the produced Baseband chip is given in Fig. 4. After layout, thesilicon area for this design is 34 mm2, including pads. The number of pins is 124.238 M. Krsti´ c, K. Maharatna, A. Troya, E. Grass, and U. Jagdhold:Fig. 4. Die photo of the Baseband chip.6 ConclusionsThis paper summarizes some research results from our Wireless Broadband Net-works project over the last ve years. The implementation of the Baseband pro-cessor compliant with the IEEE 802.11a standard was a major task. In order tofulll it, several innovative techniques were applied. In this paper the nal struc-ture of the designed Baseband processor chip is described. The general scheme isexplained and synthesis and layout results are presented. The circuitry, describedhere, is fabricated in IHP in-house 0.25 mm CMOS technology.References[1] IEEEp802.11a/d7.0,part 11: Wireless lan mediumaccess control(mac)and physicallayer (phy) specications: High speed physical layer in the 5 GHz band, Piscataway,NJ, 1999.[2] E. Grass et al., On the single-chip implementation of a hiperlan/2 and ieee 802.11acapablemodem,IEEE PersonalCommunications,vol.8, no.6, pp.4857,Dec.2001.[3] M. Krstic, A. Troya, K. Maharatna,and E. Grass, Optimizedlow-powersynchronizerdesign for the IEEE 802.11a standard, in Proc. Int. Conf. on Acoustics, Speech andSignal Processing (ICASSP), vol. II, Apr.610, 2003, pp. 333336.[4] L. Schwoerer and H. Wirz, Vlsi implementation of IEEE 802.11a physical layer, inProc. 6th Int'l. OFDM Workshop, Hamburg, Germany, 2001, pp. 28.1  28.4.Baseband Processor for IEEE 802.11a Standard with Embedded BIST 239[5] V. Mignone and A. Morello, CD3-OFDM: A novel demodulation scheme for xedandmobilereceivers,IEEETrans.onCommunications,vol.44,no.9, pp.11441151,Sept. 1996.[6] Synopsys Inc. [Online]. Available: http://www.synopsys.com/products/power/prime-power ds.pdf

CD3-OFDM: A novel demodulation scheme for xed andmobilereceivers,IEEETrans.onCommunications,vol.44,no.9,

IEEEp802.11a/d7.0,part 11: Wireless lan mediumaccess control(mac)and physical layer (phy) specications: High speed physical layer in the 5 GHz band, Piscataway,

On the single-chip implementation of a

Optimizedlow-powersynchronizer design for the IEEE 802.11a standard, in

Vlsi implementation of IEEE 802.11a physical layer, in

Baseband processor for IEEE 802.11a standard with embedded BIST

Baseband processor for IEEE 802.11a standard with embedded BIST

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