532 research outputs found
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Low power VCO-based analog-to-digital conversion
textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin
Design of a 14-bit fully differential discrete time delta-sigma modulator
Analog to digital converters play an essential role in modern mixed signal circuit design. Conventional Nyquist-rate converters require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters. A noise shaping technique is also used in DS converters in addition to oversampling to achieve a high resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this thesis, a technique to design the discrete time DS converters for 25 kHz baseband signal bandwidth will be described. The noise shaping is achieved using a switched capacitor low-pass integrator around the 1-bit quantizer loop. A latched-type comparator is used as the quantizer of the DS converter. A second order DS modulator is implemented in a TSMC 0.35 µm CMOS technology using a 3.3 V power supply. The peak signal-to-noise ratio (SNR) simulated is 87 dB; the SNDR simulated is 82 dB which corresponds to a resolution of 14 bits. The total static power dissipation is 6.6 mW
Oversampled analog-to-digital converter architectures based on pulse frequency modulation
Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development
of voltage-controlled oscillator based analog-to-digital converters (VCO-based
ADCs). Time-encoding based ADCs have become of great interest to the designer
community due to the possibility of implementing mostly digital circuits,
which are well suited for current deep-submicron CMOS processes. Within this
topic, VCO-based ADCs are one of the most promising candidates.
VCO-based ADCs have typically been analyzed considering the output phase
of the oscillator as a state variable, similar to the state variables considered in __
modulation loops. Although this assumption might take us to functional designs
(as verified by literature), it does not take into account neither the oscillation
parameters of the VCO nor the deterministic nature of quantization noise. To
overcome this issue, we propose an interpretation of these type of systems based
on the pulse frequency modulation (PFM) theory. This permits us to analytically
calculate the quantization noise, in terms of the working parameters of the system.
We also propose a linear model that applies to VCO-based systems. Thanks to
it, we can determine the different error processes involved in the digitization of
the input data, and the performance limitations which these processes direct to.
A generic model for any order open-loop VCO-based ADCs is made based on the
PFM theory. However, we will see that only the first-order case and a second order
approximation can be implemented in practice. The PFM theory also
allows us to propose novel approaches to both single-stage and multistage VCObased
architectures. We describe open-loop architectures such as VCO-based
architectures with digital precoding, PFM-based architectures that can be used
as efficient ADCs or MASH architectures with optimal noise-transfer-function
(NTF) zeros. We also make a first approach to the proposal and analysis of closed loop
architectures. At the same time, we deal with one of the main limitations of
VCOs (especially those built with ring oscillators), which is the non-linear voltage to-
frequency relation. In this document, we describe two techniques mitigate this
phenomenon.
Firstly, we propose to use a pulse width modulator in front of the VCO. This
way, there are only two possible oscillation states. Consequently, the oscillator
works linearly. To validate the proposed technique, an experimental prototype
was implemented in a 40-nm CMOS process. The chip showed noise problems
that degraded the expected resolution, but allowed us to verify that the potential
performance was close to the expected one. A potential signal-to-noise-distortion
ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming
2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar
power consumption and linearity properties.
Secondly, we used a pulse frequency modulator to implement a second ADC.
The proposed architecture is intrinsically linear and uses a digital delay line to
increase the resolution of the converter. One experimental prototype was implemented
in a 40-nm CMOS process using one of these architectures. Proper results
were measured from this prototype. These results allowed us to verify that the
PFM-based architecture could be used as an efficient ADC. The measured peak
SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an
occupied area equal to 0.08 mm2. The architecture shows a great linearity, and
in comparison to related work, it consumes less power and occupies similar area.
In general, the theoretical analyses and the architectures proposed in the
document are not restricted to any application. Nevertheless, in the case of the
experimental chips, the specifications required for these converters were linked to
communication applications (e.g. VDSL, VDSL2, or even G.fast), which means
medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low
area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva
para el diseño de convertidores analógico-digitales basados en osciladores
controlados por tensión. Los convertidores analógico-digitales con codificación
temporal han llamado la atención durante los últimos años de la comunidad de
diseñadores debido a la posibilidad de implementarlos en su gran mayoría con
circuitos digitales, los cuales son muy apropiados para los procesos de diseño
manométricos. En este ámbito, los convertidores analógico-digitales basados en
osciladores controlados por tensión son uno de los candidatos más prometedores.
Los convertidores analógico-digitales basados en osciladores controlados por
tensión han sido típicamente analizados considerando que la fase del oscilador
es una variable de estado similar a las que se observan en los moduladores __.
Aunque esta consideración puede llevarnos a diseños funcionales (como se puede
apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni
los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de
la modulación por frecuencia de pulsos. Esto nos permite calcular de forma
analítica las ecuaciones que modelan el ruido de cuantificación en función de los
parámetros de oscilación. Se propone también un modelo lineal para el análisis de
convertidores analógico-digitales basados en osciladores controlados por tensión.
Este modelo permite determinar las diferentes fuentes de error que se producen
durante el proceso de digitalización de los datos de entrada y las limitaciones
que suponen. Un modelo genérico de convertidor de cualquier orden se propone
con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una
aproximación al caso de segundo orden se pueden implementar en la práctica.
La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas
para la propuesta y el análisis tanto de arquitecturas de una sola etapa
como de arquitecturas de varias etapas construidas con osciladores controlados
por tensión. Se proponen y se describen arquitecturas en lazo abierto como son
las basadas en osciladores controlador por tensión con moduladores digitales en
la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como
convertidores analógico-digitales eficientes o arquitecturas en cascada en las que
se optimizan la distribución de los ceros en la función de transferencia del ruido.
También se realiza una aproximación a la propuesta y el análisis de arquitecturas
en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes
de los osciladores controlados por tensión (especialmente en aquellos
implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos
técnicas cuyo objetivo es mitigar esta limitación.
La primera técnica de corrección se basa en el uso de un modulador por
ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo
existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y
no se genera distorsión en los datos de salida. La técnica se propone de forma
teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo
la validación de la propuesta teórica se fabricó un prototipo experimental en un
proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la
resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá
haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una
potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de
banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con
sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo
que se mantiene el consumo así como la linealidad.
A continuación, se propone la implementación de un convertidor analógico digital
mediante un modulador por frecuencia de pulsos. La arquitectura propuesta
es intrínsecamente lineal y hace uso de una línea de retraso digital con
el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental,
se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura,
de la que se obtuvieron resultados notables. Estos resultados permitieron
verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor
analógico-digital eficiente. La arquitectura consigue una relación real
señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo
de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en
comparación con arquitecturas equivalentes, el consumo es menor mientras que
el área ocupada se mantiene similar.
En general, las aportaciones propuestas en este documento se pueden aplicar a
cualquier tipo de aplicación, independientemente de los requisitos de resolución,
ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos
fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones
(VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media
(9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja
área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman
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Linearizing techniques for voltage controlled oscillator based analog to digital converters
Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based ADCs behave like an open-loop continuous time ΔΣ modulator and achieve excellent resolution by first order noise shaping the quantization error. However, the SNDR of an open-loop VCO-based ADC is severely distortion limited by the voltage-to-frequency tuning characteristics of the VCO. This work examines various techniques that have already been proposed to overcome the VCO tuning non-linearity problem. Two new VCO-based ADC architectures, that overcome the limitations of the conventional approaches, are proposed. In the first approach, the ADC is linearized by forcing the VCO to operate at only two operating points using a front-end two level modulator. With this technique, the linearity is improved without using either a multi-bit feedback DAC or calibration. Fabricated in a 90 nm CMOS process, the prototype ADC achieves better than 71 dB SFDR and 59.1 dB SNDR in 8 MHz signal bandwidth while consuming
4.3 mW power. The ADC achieves a figure of merit of 366 fJ/conv-step, which is
comparable with other state of the art time based ADCs. In the second approach,
the need for a front-end two level modulator is obviated using linearizers, which introduce an inverse of VCO’s voltage to frequency characteristics in the signal path. A deterministic digital calibration unit runs continuously in the background and builds the inverse voltage to frequency transfer function. Implemented in a 90nm CMOS process, this on-chip calibration improves SFDR of the prototype ADC from 46 dB to more than 83 dB. The ADC consumes 4.1 mW power and achieves 73.9 dB SNDR in 5 MHz signal bandwidth resulting in an excellent figure of merit of 101 fJ/conv-step
Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs
During the past decade, SAR ADCs have enjoyed increasing prominence due to their
inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however
most of those that use non-hybrid architectures are limited to moderate (8-10 bit) resolu-
tion. Assuming an almost rail-to-rail dynamic range, comparator noise and DAC element
mismatch constraints are critical but not insurmountable at 10 bits of resolution or less in
sub-100nm processes. On the other hand, analysis shows that for medium-resolution ADCs
(11-15 bits, depending on the LSB voltage of the converter), the mismatch sizing constraint
still dominates unit capacitor sizing over the kT/C sampling noise constraint, and can only be mitigated by drawing increasingly larger capacitors.
The focus of this work is to extend the scaling benefits of the SAR architecture to medium
and higher ADC resolutions through mitigating and ultimately harnessing DAC element mismatch. This goal is achieved via a novel, completely reconfigurable capacitor DAC that allows the rearranging of capacitors to different trial groupings in the SAR cycle so that mismatch can be canceled. The DAC is implemented in a 12-bit SAR ADC in 65nm CMOS, and a nearly 2-bit improvement in linearity is demonstrated with a simple reconfiguration algorithm.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138630/1/ncolins_1.pd
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Design techniques for time based data converters
Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as digital signal processing could be used to compensate for analog inaccuracies. Calibration assisted analog-to-digital converters(ADCs), software defined radio, digital phase locked loops, etc... have all gained from improvements in the digital processing available on chip. This thesis focusses on data converters which utilize the above features of modern day CMOS processes.
The thesis is primarily divided into two parts. The first part focuses on a technique to convert the time information into a digital word. A high resolution time-to-digital converter (TDC) architecture is proposed which combines the principles of noise-shaping integrating quantizer and charge-pump to build a third-order delta-sigma TDC using a dedicated feedback DAC. Fabricated in a 0.13µm CMOS process, the prototype TDC achieves better than 71dB DR for a 2.8MHz signal bandwidth.
The second part of the thesis proposes a blind digital calibration technique to remove non-linearity in any traditional ADC architectures. The proposed technique uses the concept of downsampling and orthogonality of sinusoidal waves to estimate the harmonic distortion in ADCs and can be used to calibrate multiple harmonics simultaneously. As a proof of concept, the algorithm is demonstrated on a first-order ring oscillator based delta-sigma ADC, whose performance is harmonic distortion limited. Built in 0.13µm CMOS process, the algorithm improves the SNDR of the ADC by 39dB while improving SFDR by 45 dB
Feasibility of a 16bit, 3MSPS multibit per stage pipeline ADC using digital calibration
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.Includes bibliographical references (p. 115-116).by Matthew Louis Courcy.B.S.M.Eng
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