Analysis of the subthreshold current of pocket or halo-implanted nMOSFETs

In this work, we analyzed the subthreshold current (I/sub D/) of pocket implanted MOSFETs using extensive device simulations and experimental data. We present an analytical model for the subthreshold current applicable for any type of FET and show that the subthreshold current of nMOSFETs, which is mainly due to diffusion, is determined by the internal two-dimensional hole distribution across the device. This hole distribution is affected by the electric potential of the gate and the doping concentration in the channel. The results obtained allow accurate modelling of the subthreshold current of future generation MOS devices

Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature

A study on the influence of phosphorus implanted source/drain features on the off-state performance of transistors fabricated in thin-film crystalline silicon at low temperature is presented. Complementary Metal Oxide Semiconductor (CMOS) thin film transistors (TFTs) were fabricated on silicon-on-insulator (SOI) substrates; both NFET and PFET devices in the same p-type layer. Lightly Doped Drain (LDD) features were implemented on NFETs, and a surface-halo source barrier (N-barrier) was implemented on PFETs, using a common implant step. A new mask set was designed with fine resolution of gate offset to investigate small changes in placement of the LDD/ N-barrier structures. The focus of this investigation was the off-state characteristics of the devices; the implanted features were designed to help suppress the effects of Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Lowering (DIBL). Along with the mask design offsets, a number of process variations resulted in TFTs with different degrees of gate overlap and device symmetry. Electrical device characteristics are presented in the study, with comparisons to devices simulated using Silvaco ® Atlas

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Tunnel Field Effect Transistors:from Steep-Slope Electronic Switches to Energy Efficient Logic Applications

The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteristics. The main differences of a Tunnel FET with respect to a conventional MOSFET is pointed out and the differences have been explained. A compact DC/AC model has been developed which is capable of describing the I-V characteristics in all regimes of operation. The model takes in to account ambi-polarity, drain side breakdown and all tunneling related physics. A temperature dependence is also added to the model to study the temperature independent behavior of tunneling. The model was further implemented in a Verilog-A based circuit simulator. Following calibration to experimental results of Silicon and strained-Silicon TFETs, the model has been also used to benchmark against a standard CMOS node for digital and analog applications. The circuits built with Tunnel FETs showed interesting temperature behavior which was superior to the compared CMOS node. In the same work, we also explore and propose solutions for using TFETs for low power memory applications. Both volatile and non-volatile memory concepts are investigated and explored. The application of a Tunnel FET as a capacitor-less memory has been experimentally demonstrated for the first time. New device concepts have been proposed and process flows for the same are developed to realize them in the clean room in EPFL

Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability

One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it is necessary to transfer reliably the MOSFET statistical variability information into compact models to facilitate variability aware design practice. The aim of this project is the development of a statistical extraction methodology essential to capture statistical variability with optimum set of parameters particularly in industry standard compact model BSIM. This task is accomplished by using a detailed study on the sensitivity analysis of the transistor current in respect to key parameters in compact model in combination with error analysis of the fitted Id-Vg characteristics. The key point in the developed direct statistical compact model strategy is that the impacts of statistical variability can be captured in device characteristics by tuning a limited number of parameters and keeping the values for remaining major set equal to their default values obtained from the “uniform” MOSFET compact model extraction. However, the statistical compact model extraction strategies will accurately represent the distribution and correlation of the electrical MOSFET figures of merit. Statistical compact model parameters are generated using statistical parameter generation techniques such as uncorrelated parameter distributions, principal component analysis and nonlinear power method. The accuracy of these methods is evaluated in comparison with the results obtained from ‘atomistic’ simulations. The impact of the correlations in the compact model parameters has been analyzed along with the corresponding transistor figures of merit. The accuracy of the circuit simulations with different statistical compact model libraries has been studied. Moreover, the impact of the MOSFET width/length on the statistical trend of the optimum set of statistical compact model parameters and electrical figures of merit has been analyzed with two methods to capture geometry dependencies in proposed statistical models

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V

Statistical modelling of nano CMOS transistors with surface potential compact model PSP

The development of a statistical compact model strategy for nano-scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current-voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input-output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized

Interpretation and Physical Modeling of Electronic Transport and Defect States in IGZO Thin-Film Transistors

This work is a comprehensive study on the interpretation and modeling of electronic transport behavior and defect states in indium-gallium-zinc-oxide (IGZO) TFTs. Key studies have focused on advancing the state of IGZO TFTs by addressing several challenges in device stability, scaling, and device modeling. These studies have provided new insight on the associated mechanisms and have resulted in the realization of scaled thin-film transistors that exhibit excellent electrical performance and stability. This work has demonstrated the ability to scale the conventional inverted staggered IGZO TFT down to one micron channel length, with excellent on-state and off-state performance where the VT ≈1 V, µeff =12 cm2/Vs, Ileak ≤ 10-12 A/µm and SS ≈ 160 mV/dec. The working source/drain electrodes are direct metal contact regions to the IGZO, which requires several microns of gate overlap to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. New results utilizing ion implantation for self-aligned source/drain regions present a path towards submicron channel length. This strategy offers a reduction in channel length as well as parasitic capacitance, which translates to improvement in RC delay and associated voltage losses due to charge-sharing. The realization of self-aligned TFTs using boron ion implantation for selective activation was introduced in a first-time report of boron-doped IGZO. Cryogenic measurements made on long-channel devices has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. A completely new device model using Silvaco Atlas has been established which properly accounts for the role of donor-like oxygen vacancy defects, acceptor-like band-tail states, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The developed model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. A power-law fit for the µch = f(T) relationship, which resembles 〖μ ~ T〗^((+3)⁄2) behavior consistent with ionized defect scattering. The mobility model is expressly independent of carrier concentration, without dependence on the applied gate bias. The device model is consistent with a compact model developed for circuit simulation (SPICE) that has been recently refined to include on-state and off-state operation. While IGZO is the only AOS technology mature enough for commercialization, the effective electron channel mobility µeff ~ 10 cm2/Vs presents a performance limitation. Other candidate AOS materials which have higher reported channel mobility values have also been investigated; specifically, indium-tungsten-oxide (IWO) and indium-gallium-tin-oxide (ITGO). These investigations serve as preliminary studies; device characteristics support the claims of high channel mobility; however the influence of defect states clearly indicates the need for further process development. The advancements realized in IGZO TFTs in this work will serve as a foundation for these alternative AOS materials

Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces

Until the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS.Jusqu’au début des années 2000, les règles de scaling de Dennard ont permis de réaliser des gains en performance tout en conservant la structure de la brique de base transistor d’une génération technologique à la suivante. Cependant, cette approche conservatrice a d’ores et déjà atteint ses limites, comme en témoigne l’introduction de la contrainte mécanique pour les générations sub-130nm, et les empilements de grille métal/high-k pour les nœuds sub-65nm. Malgré l’introduction de diélectriques à forte permittivité, des limites en termes de courants de fuite de grille et de fiabilité ont ralenti la diminution de l’épaisseur équivalente d’oxyde (EOT). De façon concommitante, la diminution de la tension d’alimentation (VDD) est devenue une priorité afin de réduire la densité de puissance dissipée dans les circuits intégrés. D’où le défi actuel: comment continuer de réduire à la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dégrader le rapport de performances aux états passant et bloqué (ON et OFF) ? Diverses solutions peuvent être proposées, passant par des architectures s’éloignant du MOSFET conventionnel à canal Si avec source et drain dopés tel que défini en 1960. Une approche consiste en réaliser une augmentation du courant passant (ION) tout en laissant le courant à l’état bloqué (IOFF) et la tension de seuil (Vth) inchangés. Concrètement, deux options sont considérées en détail dans ce manuscrit à travers une revue de leurs motivations historiques respectives, les résultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) à leur mise en œuvre : i/ la réduction de la résistance parasite extrinsèque par l’introduction de source et drain métalliques (architecture transistor à barrière Schottky) ; ii/ la réduction de la résistance de canal intrinsèque par l’introduction de matériaux à haute mobilité à base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intégration Dual Channel n-sSi/p-sSiGe). En particulier, nous étudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivé par: la préservation de l’intégrité électrostatique pour les nœuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs à base de Ge (qui est un matériau à faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal à base de Germanium peut être avantageuse vis-à-vis du CMOS Silicium conventionnel

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization