Integrated capacitors for conductive lithographic film circuits

This paper reports on fabrication of low-value embedded capacitors in conductive lithographic film (CLF) circuit boards. The CLF process is a low-cost and high speed manufacturing technique for flexible circuits and systems. We report on the construction and electrical characteristics of CLF capacitor structures printed onto flexible substrates. These components comprise a single polyester dielectric layer, which separates the printed electrode films. Multilayer circuit boards with printed components and interconnect can be fabricated using this technique

High Input/output Density Optoelectronic Probe Card For Wafer-level Test Of Electrical And Optical Interconnect Components, Methods Of Fabrication, And Methods Of Use

Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.Georgia Tech Research Corporatio

Devices Having Compliant Wafer-level Input/output Interconnections And Packages Using Pillars And Methods Of Fabrication Thereof

Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.Georgia Tech Research Corporatio

Bubble memory module

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses

A LVDS Serial AER Link

Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows to analyse a LVDS Serial AER link. The interface allows up to 0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0

LVDS Serial AER Link performance

Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows analysing a LVDS Serial AER link produced by a Spartan 3 FPGA, or by a commercial LVDS transceiver. The interface allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0

Quantifying SMT Decoupling Capacitor Placement in dc Power-Bus Design for Multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach

Estimating the Noise Mitigation Effect of Local Decoupling in Printed Circuit Boards

Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bus noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling

Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output