An embedded system for evoked biopotential acquisition and processing

This work presents an autonomous embedded system for evoked biopotential acquisition and processing. The system is versatile and can be used on different evoked potential scenarios like medical equipments or brain computer interfaces, fulfilling the strict real-time constraints that they impose. The embedded system is based on an ARM9 processor with capabilities to port a real-time operating system. Initially, a benchmark of the Windows CE operative system running on the embedded system is presented in order to find out its real-time capability as a set. Finally, a brain computer interface based on visual evoked potentials is implemented. Results of this application recovering visual evoked potential using two techniques: the fast Fourier transform and stimulus locked inter trace correlation, are also presented.Fil: Garcia, Pablo Andres. Universidad Nacional de la Plata. Facultad de Ingeniería. Departamento de Electrotecnia. Laboratorio de Electrónica Industrial, Control e Instrumentación; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Spinelli, Enrique Mario. Universidad Nacional de la Plata. Facultad de Ingeniería. Departamento de Electrotecnia. Laboratorio de Electrónica Industrial, Control e Instrumentación; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Toccaceli, Graciela Mabel. Universidad Nacional de la Plata. Facultad de Ingeniería. Departamento de Electrotecnia. Laboratorio de Electrónica Industrial, Control e Instrumentación; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentin

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

On the Application of a Monolithic Array for Detecting Intensity-Correlated Photons Emitted by Different Source Types

It is not widely appreciated that many subtleties are involved in the accurate measurement of intensity-correlated photons; even for the original experiments of Hanbury Brown and Twiss (HBT). Using a monolithic 4x4 array of single-photon avalanche diodes (SPADs), together with an off-chip algorithm for processing streaming data, we investigate the difficulties of measuring second-order photon correlations g2 in a wide variety of light fields that exhibit dramatically different correlation statistics: a multimode He-Ne laser, an incoherent intensity-modulated lamp-light source and a thermal light source. Our off-chip algorithm treats multiple photon-arrivals at pixel-array pairs, in any observation interval, with photon fluxes limited by detector saturation, in such a way that a correctly normalized g2 function is guaranteed. The impact of detector background correlations between SPAD pixels and afterpulsing effects on second-order coherence measurements is discussed. These results demonstrate that our monolithic SPAD array enables access to effects that are otherwise impossible to measure with stand-alone detectors.Comment: 17 pages, 6 figure

A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Four-dimensional dynamic flow measurement by holographic particle image velocimetry

The ultimate goal of holographic particle image velocimetry (HPIV) is to provide space- and time-resolved measurement of complex flows. Recent new understanding of holographic imaging of small particles, pertaining to intrinsic aberration and noise in particular, has enabled us to elucidate fundamental issues in HPIV and implement a new HPIV system. This system is based on our previously reported off-axis HPIV setup, but the design is optimized by incorporating our new insights of holographic particle imaging characteristics. Furthermore, the new system benefits from advanced data processing algorithms and distributed parallel computing technology. Because of its robustness and efficiency, for the first time to our knowledge, the goal of both temporally and spatially resolved flow measurements becomes tangible. We demonstrate its temporal measurement capability by a series of phase-locked dynamic measurements of instantaneous three-dimensional, three-component velocity fields in a highly three-dimensional vortical flow--the flow past a tab

Comparison of the performance of 3G security algorithms in the NAS layer

Cryptographic functionality implementation approaches have evolved over time, first, for running security software on a general-purpose processor, second, employing a separate security co-processor ,and third, using built-in hardware acceleration for security that is a part of a multi-core CPU system. The aim of this study is to do performance tests in order to examine the boost provided by accelerating KASUMI cryptographic functions on a multi-core Cavium OCTEON processor over the same non-accelerating cryptographic algorithm implemented in software. Analysis of the results shows that the KASUMI SW implementation is much slower than the KASUMI HW-based implementation and this difference increases gradually as the packet size is doubled. In detailed comparisons between the encryption and decryption functions, the result indicates that at a lower data rate, neither of the KASUMI implementations shows much difference between encryption or decryption processing, regardless of the increase in the number of data packets that are being processed. When all the 16 cores of the OCTEAN processor are populated, as the number of core increases, the number of processing cycles decreases accordingly. Another observation was that when the number of cores in use exceeds 5 cores, it doesn’t make much difference to the number of decrease of processing cycles. This work illustrates the potential that up to sixteen cnMIPS cores integrated into a single-chip OCTEON processor provides for HW- and SW-based KASUMI implementations.fi=Opinnäytetyö kokotekstinä PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=Lärdomsprov tillgängligt som fulltext i PDF-format

Software Defined DCF77 Receiver

This paper shows the solution of time stamp software defined receiver integration into low cost com-mercial devices. The receiver is based on a general pur-pose processor and its analog to digital converter. The amplified signal from a narrow-band antenna is connected to the converter and no complicated filtration has to be used. All signal processing is digitally provided by the processor. During signal reception, the processor stays available for its main tasks and signal processing con-sumes only a small part of its computational power