A zero-cost, real-time, Windows signal laboratory

This paper introduces a Windows-based signal capture, display, and waveform synthesis package called “Win-eLab”. The software is able to run on a conventional desktop or laptop with no additional hardware, and can perform real-time Fourier analysis on audio-frequency signals. This paper is intended as an introduction to Win-eLab, aimed at motivating further use of it in both teaching and self-directed learning contexts. The use of the software to familiarize students with the concept of “laboratory” instrumentation is discussed, as well as the usefulness of a simultaneous time-domain/frequency-domain display for understanding signals, particularly in signal processing and communications systems courses. It is anticipated that applications may extend beyond electrical & electronic engineering – for example, as an aid to understanding mechanical vibrations, acoustics, and in other discipline areas

Towards Multi-Modal Interactions in Virtual Environments: A Case Study

We present research on visualization and interaction in a realistic model of an existing theatre. This existing ‘Muziek¬centrum’ offers its visitors information about performances by means of a yearly brochure. In addition, it is possible to get information at an information desk in the theatre (during office hours), to get information by phone (by talking to a human or by using IVR). The database of the theater holds the information that is available at the beginning of the ‘theatre season’. Our aim is to make this information more accessible by using multi-modal accessible multi-media web pages. A more general aim is to do research in the area of web-based services, in particu¬lar interactions in virtual environments

Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

Drawing OWL 2 ontologies with Eddy the editor

In this paper we introduce Eddy, a new open-source tool for the graphical editing of OWL~2 ontologies. Eddy is specifically designed for creating ontologies in Graphol, a completely visual ontology language that is equivalent to OWL~2. Thus, in Eddy ontologies are easily drawn as diagrams, rather than written as sets of formulas, as commonly happens in popular ontology design and engineering environments. This makes Eddy particularly suited for usage by people who are more familiar with diagramatic languages for conceptual modeling rather than with typical ontology formalisms, as is often required in non-academic and industrial contexts. Eddy provides intuitive functionalities for specifying Graphol diagrams, guarantees their syntactic correctness, and allows for exporting them in standard OWL 2 syntax. A user evaluation study we conducted shows that Eddy is perceived as an easy and intuitive tool for ontology specification

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Intelligent tutoring systems for systems engineering methodologies

The general goal is to provide the technology required to build systems that can provide intelligent tutoring in IDEF (Integrated Computer Aided Manufacturing Definition Method) modeling. The following subject areas are covered: intelligent tutoring systems for systems analysis methodologies; IDEF tutor architecture and components; developing cognitive skills for IDEF modeling; experimental software; and PC based prototype

Stakeholder Perspectives to Support Graphical User Interface Design for Children with Autism Spectrum Disorder: A Qualitative Study

[Abstract] The development of digital supports for people with autism has increased considerably in recent years. Technology designers and developers have interpreted the needs and learning styles of people with autism in different ways. As a result, there are generic, non-specific or heterogeneous guidelines for the design and development of technology for people with autism. This study aims to identify and describe the recommended elements to support graphical user interface design for children with Autism Spectrum Disorder (ASD), considering the stakeholders’ perspective, engaged in a computer application development. A qualitative, longitudinal, multicentre study was carried out. A sample of 39 participants belonging to four groups of stakeholders participated: children with autism, family members, professionals with experience in the intervention with children with autism, and professionals with expertise in the design and development of assistive technology. The techniques used to formalise the collection of information from participants were semi-structured interviews and observation. MAXQDA 2020 software (Verbi Software, Berlin, Germany) was used to analyse the data. The result is a guide with suggestions to support an interface design that emerges from the stakeholder perspectives. This study provides useful information to offer alternatives for children with ASD and facilitate the understanding of daily life.The authors disclose the receipt of the following financial support for the research, authorship, and/or publication of this article: all the economic costs involved in the study will be borne by the research team. We wish to acknowledge the support received from the Centro de Investigación de Galicia “CITIC”, funded by Xunta de Galicia and the European Union (European Regional Development Fund- Galicia 2014–2020 Program), by grant ED431G 2019/01. The diffusion and publication of this research are funded by the CITIC. This study was partially supported by the Orange Foundation in Spain. Moreover, the author P.C.-M. obtained a scholarship (Ref. ED481A-2019/069), and the author M.d.C.M.-D. (Ref. ED481A 2018/205) to develop a PhD thesis. In addition, this research had the support by the National Program of R + D + i oriented to the Challenges of Society 2019 (PID2019-104323RB-C33)