Output Filter Aware Optimization of the Noise Shaping Properties of {\Delta}{\Sigma} Modulators via Semi-Definite Programming

The Noise Transfer Function (NTF) of {\Delta}{\Sigma} modulators is typically designed after the features of the input signal. We suggest that in many applications, and notably those involving D/D and D/A conversion or actuation, the NTF should instead be shaped after the properties of the output/reconstruction filter. To this aim, we propose a framework for optimal design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite programming. Some examples illustrate how in practical cases the proposed strategy can outperform more standard approaches.Comment: 14 pages, 18 figures, journal. Code accompanying the paper is available at http://pydsm.googlecode.co

Evaluation of Sigma-Delta-over-Fiber for High-Speed Wireless Applications

Future mobile communication networks aim to increase the communication speed,\ua0provide better reliability and improve the coverage. It needs to achieve all of these enhancements, while the number of users are increasing drastically. As a result, new base-station (BS) architectures where the signal processing is centralized and wireless access is provided through multiple, carefully coordinated remote radio heads are needed. Sigma-delta-over-fiber (SDoF) is a communication technique that can address both requirements and enable very low-complexity, phase coherent remote radio transmission, while transmitting wide-band communication signals with high quality. This thesis investigates the potential and limitations of SDoF communication links as an enabler for future mobile networks.In the first part of the thesis, an ultra-high-speed SDoF link is realized by using state-of-the-art vertical-cavity surface-emitting-lasers (VCSEL). The effects of VCSEL characteristics on such links in terms of signal quality, energy efficiency and potential lifespan is investigated. Furthermore, the potential and limitations of UHS-SDoF are evaluated with signals having various parameters. The results show that, low-cost, reliable, energy efficient, high signal quality SDoF links can be formed by using emerging VCSEL technology. Therefore, ultra-high-speed SDoF is a very promising technique for beyond 10~GHz communication systems.In the second part of the thesis, a multiple-input-multiple-output (MIMO) communication testbed with physically separated antenna elements, distributed-MIMO, is formed by multiple SDoF links. It is shown that the digital up-conversion, performed with a shared local-oscillator/clock at the central unit, provides excellent phase coherency between the physically distributed antenna elements. The proposed testbed demonstrates the advantages of SDoF for realizing distributed MIMO systems and is a powerful tool to perform various communication experiments in real environments.In general, SDoF is a solution for the downlink of a communication system, i.e. from central unit to remote radio head, however, the low complexity and low cost requirement of the remote radio heads makes it difficult to realize the uplinks of such systems. The third part of this thesis proposes an all-digital solution for realizing complementary uplinks for SDoF systems. The proposed structure is extensively investigated through simulations and measurements and the results demonstrate that it is possible realize all-digital, duplex, optical communication links between central units and remote radio heads.In summary, the results in this thesis demonstrate the potential of SDoF for wideband, distributed MIMO communication systems and proposes a new architecture for all-digital duplex communication links. Overall, the thesis shows that SDoF technique is powerful technique for emerging and future mobile communication networks, since it enables a centralized structure with low complexity remote radio heads and provides high signal quality

Parallelization of Bandpass Sigma-Delta Modulators for Class-S Digital Power Amplifiers

In this paper a new technique of utilizing parallel sigma delta modulation for high frequency switch mode digital power amplifiers is presented. This approach allows achieving a factor of two increase of a digital logic speed for band-pass SDM with minor adjustments made. A universal scheme for a SDM system transformation is provided. Since the transformation scheme is established, a parallel low-pass SDM, expandable to a factor of four clock frequency reduction is designed. The parallelization of a low pass SDM however requires modification on the form of a Noise Transfer Function in order to preserve desired speed of a digital logic. This can affect the overall performance of the SDM. The derivation of the systems is provided through analysis of discrete time domain equations. The method is validated through simulations

A programmable CMOS decimator for sigma-delta analog-to-digital converter and charge pump circuits

PROGRAMMABLE DECIMATOR FOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER: In this work a programmable decimator design has been presented in 1.5 μm n-well CMOS process for integration with an existing modulator to form a sigma-delta analog-to-digital converter (ADC). The decimator is implemented using a second order Cascaded Integrator Comb (CIC) filter and can be programmed to work with two different oversampling ratios of 64 and 16. The input to the decimator is provided from a first order modulator. With oversampling ratios of 64 and 16, an output resolution of 10-bit and 7-bit, respectively are achieved for the ADC. The ADC can be operated with an oversampling clock frequency of up to 8 MHz and with an input signal bandwidth of up to 65 KHz. An in-built clock divider circuit has been designed which generates two output clocks whose frequencies are equal to the input clock frequency divided by the oversampling ratios 64 and 16. CHARGE PUMP CIRCUITS: The charge pump CMOS circuits are presented which are designed based on a new technique of internal clock voltage boosting. Four and six-stage charge pumps are implemented in 1.5 μm n-well CMOS process. The charge pump circuits can be operated in 1.2 V - 3 V power supply voltage range. Outputs of 12.5 V and 17.8 V are measured from four and six-stage charge pumps, respectively with a 3 V power supply. The charge pump circuits can also be used to generate clock voltages higher than the input clock voltage. In the present design, clock voltages of 8 V and 11 V have been generated from four-stage and six-stage charge pumps, respectively which are nearly 2.5 and 4 times the input clock voltage of 3 V. The technique of boosting the clock internally has been applied in implementation of a revised version of battery powered Bio-implantable Electrical Stimulation System (BESS) integrated circuit

Correction of errors and harmonic distortion in pulse-width modulation of digital signals

Article number 153991Pulse-Width (PW) modulation is widely used in those applications where an analog or digital signal has to be encoded in the time domain as a binary stream, such as switched-mode power amplifiers in transmitters of modern telecommunication standards, high-resolution digital signal conversion using single-bit digital-to-analog converters, and many others. Due to the fact that digital signals are sampled in the time domain, the quality of the resulting PW modulated waveforms is worsened by harmonic distortion. Multilevel PW modulation has been proposed to reduce these adverse effects, but the modulated waveform is no longer binary. In this paper, the mechanisms by which harmonic distortion is produced are analyzed. As a result, the distortion terms are mathematically quantified and used to correct the errors. Note that a correction network based on a simple subtraction of the distortion terms from the PW modulated signal would produce a waveform that would no longer be binary. The proposed correction network is implemented in the digital domain and, by means of a sigma-delta modulator, preserves the binary feature of the PW modulated output.Ministerio de Ciencia, Innovación y Universidades (España) RTI201- 099189-B-C2

Asynchronous spiking neurons, the natural key to exploit temporal sparsity

Inference of Deep Neural Networks for stream signal (Video/Audio) processing in edge devices is still challenging. Unlike the most state of the art inference engines which are efficient for static signals, our brain is optimized for real-time dynamic signal processing. We believe one important feature of the brain (asynchronous state-full processing) is the key to its excellence in this domain. In this work, we show how asynchronous processing with state-full neurons allows exploitation of the existing sparsity in natural signals. This paper explains three different types of sparsity and proposes an inference algorithm which exploits all types of sparsities in the execution of already trained networks. Our experiments in three different applications (Handwritten digit recognition, Autonomous Steering and Hand-Gesture recognition) show that this model of inference reduces the number of required operations for sparse input data by a factor of one to two orders of magnitudes. Additionally, due to fully asynchronous processing this type of inference can be run on fully distributed and scalable neuromorphic hardware platforms

Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

A Current-Mode Multi-Channel Integrating Analog-to-Digital Converter

Multi-channel analog to digital converters (ADCs) are required where signals from multiple sensors can be digitized. A lower power per channel for such systems is important in order that when the number of channels is increased the power does not increase drastically. Many applications require signals from current output sensors, such as photosensors and photodiodes to be digitized. Applications for these sensors include spectroscopy and imaging. The ability to digitize current signals without converting currents to voltages saves power, area, and the design time required to implement I-to-V converters. This work describes a novel and unique current-mode multi-channel integrating ADC which processes current signals from sensors and converts it to digital format. The ADC facilitates the processing of current analog signals without the use of transconductors. An attempt has been made also to incorporate voltage-mode techniques into the current-mode design so that the advantages of both techniques can be utilized to augment the performance of the system. Additionally since input signals are in the form of currents, the dynamic range of the ADC is less dependant on the supply voltage. A prototype 4-channel ADC design was fabricated in a 0.5-micron bulk CMOS process. The measurement results for a 10Ksps sampling rate include a DNL, which is less than 0.5 LSB, and a power consumption of less than 2mW per channel

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Theory and applications of delta-sigma analogue-to-digital converters without negative feedback

Analog-to-digital converters play a crucial role in modern audio and communication design. Conventional Nyquist converters are suitable only for medium resolutions and require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can achieve high resolutions (>20bits) and can be implemented using straightforward, high-tolerance analog components. In conventional oversampled modulators, negative feedback is applied in order to control the dynamic behavior of a system and to realize the attenuation of the quantization noise in the signal band due to noise shaping. However, feedback can also introduce undesirable effects such as limit cycles, jitter problems in continuous-time topologies, and infinite impulse responses. Additionally, it increases the system complexity due to extra circuit components such as nonlinear multi-bit digital-to-analog converters in the feedback path. Moreover, in certain applications such as wireless, biomedical sensory, or microphone implementations feedback cannot be applied. As a result, the main goal of this thesis is to develop sigma-delta data converters without feedback. Various new delta-sigma analog-to-digital converter topologies are explored their mathematical models are presented. Simulations are carried out to validate these models and to show performance results. Specifically, two topologies, a first-order and a second-order oscillator-based delta-sigma modulator without feedback are described in detail. They both can be implemented utilizing VCOs and standard digital gates, thus requiring only few components. As proof of concept, two digital microphones based on these delta-sigma converters without feedback were implemented and experimental results are given. These results show adequate performance and provide a new approach of measuring