A new BIST scheme for low-power and high-resolution DAC testing

A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals

Testing high resolution SD ADC’s by using the noise transfer function

A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, 4th order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation

On-chip evaluation of oscillation-based-test output signals for switched-capacitor circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approac

Built-In Self-Test for Automatic Analog Frequency Response Measurement

Abstract-We present a Built-In Self-Test (BIST) approach based on direct digital synthesizer (DDS) for functional test of analog circuitry in mixed-signal systems. DDS with delta-sigma noise shaping is used to generate test signals with different frequencies and phases. The DDS-based BIST hardware implementation can sweep the frequencies through the interested bands and thus measure the frequency response of the analog circuit. The proposed BIST approach has been implemented in Verilog and synthesized into a Field Programmable Gate Array (FPGA). The actual device under test (DUT) was implemented using a Field Programmable Analog Array (FPAA) to form a complete BIST testbed for analog functional tests

A re-configurable pipeline ADC architecture with built-in self-test techniques

High-performance analog and mixed-signal integrated circuits are integral parts of today\u27s and future networking and communication systems. The main challenge facing the semiconductor industry is the ability to economically produce these analog ICs. This translates, in part, into the need to efficiently evaluate the performance of such ICs during manufacturing (production testing) and to come up with dynamic architectures that enable the performance of these ICs to be maximized during manufacturing and later when they\u27re operating in the field. On the performance evaluation side, this dissertation deals with the concept of Built-In-Self-Test (BIST) to allow the efficient and economical evaluation of certain classes of high-performance analog circuits. On the dynamic architecture side, this dissertation deals with pipeline ADCs and the use of BIST to dynamically, during production testing or in the field, re-configure them to produce better performing ICs.;In the BIST system proposed, the analog test signal is generated on-chip by sigma-delta modulation techniques. The performance of the ADC is measured on-chip by a digital narrow-band filter. When this system is used on the wafer level, significant testing time and thus testing cost can be saved.;A re-configurable pipeline ADC architecture to improve the dynamic performance is proposed. Based on dynamic performance measurements, the best performance configuration is chosen from a collection of possible pipeline configurations. This basic algorithm can be applied to many pipeline analog systems. The proposed grouping algorithm cuts down the number of evaluation permutation from thousands to 18 for a 9-bit ADC thus allowing the method to be used in real applications.;To validate the developments of this dissertation, a 40MS/s 9-bit re-configurable pipeline ADC was designed and implemented in TSMC\u27s 0.25mum single-poly CMOS digital process. This includes a fully differential folded-cascode gain-boosting operational amplifier with high gain and high unity-gain bandwidth. The experimental results strongly support the effectiveness of reconfiguration algorithm, which provides an average of 0.5bit ENOB improvement among the set of configurations. For many applications, this is a very significant performance improvement.;The BIST and re-configurability techniques proposed are not limited to pipeline ADCs only. The BIST methodology is applicable to many analog systems and the re-configurability is applicable to any analog pipeline system

A BIST solution for frequency domain characterization of analog circuits

This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1storder ÓÄ modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35ìm-3.3V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of [email protected] (1MHz clock) has been demonstrated.Gobierno de España TEC2007-68072/MIC, TSI 020400- 2008-71Catrene European Project 2A105SR

Built-in self-test and self-calibration for analog and mixed signal circuits

Analog-to-digital converters (ADC) are one of the most important components in modern electronic systems. In the mission-critical applications such as automotive, the reliability of the ADC is critical as the ADC impacts the system level performance. Due to the aging effect and environmental changes, the performance of the ADC may degrade and even fail to meet the accuracy requirement over time. Built-in self-test (BIST) and self-calibration are becoming the ultimate solution to achieve lifetime reliability. This dissertation introduces two ADC testing algorithms and two ADC built-in self-test circuit implementations to test the ADC integral nonlinearity (INL) and differential nonlinearity (DNL) on-chip. In the first testing algorithm, the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) is developed for ADC built-in self-test, which eliminates the need for precision stimulus and reduces the overall test time. In this algorithm, the ADC is tested twice with a nonlinear ramp, instead of using a linear ramp signal. Therefore, the stimulus can be easily generated on-chip in a low-cost way. For the two ramps, there is a constant voltage shift in between. As the input stimulus linearity is completely relaxed, there is no requirement on the waveform of the input stimulus as long as it covers the ADC input range. In the meantime, the high-resolution ADC linearity is modeled with segmented parameters, which reduces the number of samples required for achieving high-precision test, thus saving the test time. As a result, the USER-SMILE algorithm is able to use less than 1 sample/code nonlinear stimulus to test high resolution ADCs with less than 0.5 least significant bit (LSB) INL estimation error, achieving more than 10-time test time reduction. This algorithm is validated with both board-level implementation and on-chip silicon implementation. The second testing algorithm is proposed to test the INL/DNL for multi-bit-per-stages pipelined ADCs with reduced test time and better test coverage. Due to the redundancy characteristics of multi-bit-per-stages pipelined ADC, the conventional histogram test cannot estimate and calibrate the static linearity accurately. The proposed method models the pipelined ADC nonlinearity as segmented parameters with inter-stage gain errors using the raw codes instead of the final output codes. During the test phase, a pure sine wave is sent to the ADC as the input and the model parameters are estimated from the output data with the system identification method. The modeled errors are then removed from the digital output codes during the calibration phase. A high-speed 12-bit pipelined ADC is tested and calibrated with the proposed method. With only 4000 samples, the 12-bit ADC is accurately tested and calibrated to achieve less than 1 LSB INL. The ADC effective number of bits (ENOB) is improved from 9.7 bits to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by more than 20dB after calibration. In the first circuit implementation, a low-cost on-chip built-in self-test solution is developed using an R2R digital-to-analog converter (DAC) structure as the signal generator and the voltage shift generator for ADC linearity test. The proposed DAC is a subradix-2 R2R DAC with a constant voltage shift generation capability. The subradix-2 architecture avoids positive voltage gaps caused by mismatches, which relaxes the DAC matching requirements and reduces the design area. The R2R DAC based BIST circuit is fabricated in TSMC 40nm technology with a small area of 0.02mm^2. Measurement results show that the BIST circuit is capable of testing a 15-bit ADC INL accurately with less than 0.5 LSB INL estimation error. In the second circuit implementation, a complete SAR ADC built-in self-test solution using the USER-SMILE is developed and implemented in a 28nm automotive microcontroller. A low-cost 12-bit resistive DAC with less than 12-bit linearity is used as the signal generator to test and calibrate a SAR ADC with a target linearity of 12 bits. The voltage shift generation is created inside the ADC with capacitor switching. The entire algorithm processing unit for USER-SMILE algorithm is also implemented on chip. The final testing results are saved in the memory for further digital calibration. Both the total harmonic distortion (THD) and the SFDR are improved by 20dB after calibration, achieving -84.5dB and 86.5dB respectively. More than 700 parts are tested to verify the robustness of the BIST solution

IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC

This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain, source-drain, gate-source and gate-substrate bridging faults are injected using fault injection transistors. All the four faults cause varying fault currents and are successfully detected by the BICS at a good operation speed. The BICS have a negligible impact on the performance of the modulator and an external pin is provided to completely cut-off the BICS from the modulator. The modulator was designed and fabricated in 1.5 μm n-well CMOS process. The decimator was designed on Altera\u27s FLEXE20K board using Verilog. The modulator and decimator were assembled together to form a sigma-delta ADC