Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures

abstract: Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed. Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced. Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method. Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed. Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Advanced deep space communication systems study Final report

Deep space communication system requirements for period 1970 to 198

Antenna integration for wireless and sensing applications

As integrated circuits become smaller in size, antenna design has become the size limiting factor for RF front ends. The size reduction of an antenna is limited due to tradeoffs between its size and its performance. Thus, combining antenna designs with other system components can reutilize parts of the system and significantly reduce its overall size. The biggest challenge is in minimizing the interference between the antenna and other components so that the radiation performance is not compromised. This is especially true for antenna arrays where the radiation pattern is important. Antenna size reduction is also desired for wireless sensors where the devices need to be unnoticeable to the subjects being monitored. In addition to reducing the interference between components, the environmental effect on the antenna needs to be considered based on sensors' deployment. This dissertation focuses on solving the two challenges: 1) designing compact multi-frequency arrays that maintain directive radiation across their operating bands and 2) developing integrated antennas for sensors that are protected against hazardous environmental conditions. The first part of the dissertation addresses various multi-frequency directive antennas arrays that can be used for base stations, aerospace/satellite applications. A cognitive radio base station antenna that maintains a consistent radiation pattern across the operating frequencies is introduced. This is followed by multi-frequency phased array designs that emphasize light-weight and compactness for aerospace applications. The size and weight of the antenna element is reduced by using paper-based electronics and internal cavity structures. The second part of the dissertation addresses antenna designs for sensor systems such as wireless sensor networks and RFID-based sensors. Solar cell integrated antennas for wireless sensor nodes are introduced to overcome the mechanical weakness posed by conventional monopole designs. This can significantly improve the sturdiness of the sensor from environmental hazards. The dissertation also introduces RFID-based strain sensors as a low-cost solution to massive sensor deployments. With an antenna acting as both the sensing device as well as the communication medium, the cost of an RFID sensor is dramatically reduced. Sensors' strain sensitivities are measured and theoretically derived. Their environmental sensitivities are also investigated to calibrate them for real world applications.Ph.D.Committee Chair: Tentzeris, Emmanouil; Committee Member: Akyildiz, Ian; Committee Member: Allen, Mark; Committee Member: Naishadham, Krishna; Committee Member: Peterson, Andrew; Committee Member: Wang, Yan

Optical Yagi-Uda nanoantennas

Conventional antennas, which are widely employed to transmit radio and TV signals, can be used at optical frequencies as long as they are shrunk to nanometer-size dimensions. Optical nanoantennas made of metallic or high-permittivity dielectric nanoparticles allow for enhancing and manipulating light on the scale much smaller than wavelength of light. Based on this ability, optical nanoantennas offer unique opportunities regarding key applications such as optical communications, photovoltaics, non-classical light emission, and sensing. From a multitude of suggested nanoantenna concepts the Yagi-Uda nanoantenna, an optical analogue of the well-established radio-frequency Yagi-Uda antenna, stands out by its efficient unidirectional light emission and enhancement. Following a brief introduction to the emerging field of optical nanoantennas, here we review recent theoretical and experimental activities on optical Yagi-Uda nanoantennas, including their design, fabrication, and applications. We also discuss several extensions of the conventional Yagi-Uda antenna design for broadband and tunable operation, for applications in nanophotonic circuits and photovoltaic devices

SiGe BiCMOS ICs for X-Band 7-Bit T/R module with high precision amplitude and phase control

Over the last few decades, phased array radar systems had been utilizing Transmit/Receive (T/R) modules implemented in III-V semiconductor based technologies. However, their high cost, size, weight and low integration capability created a demand for seeking alternative solutions to realize T/R modules. In recent years, SiGe BiCMOS technologies are rapidly growing their popularity in T/R module applications by virtue of meeting high performance requirements with more reduced cost and power dissipation with respect to III-V technologies. The next generation phased array radar systems require a great number of fully integrated, high yield, small-scale and high accuracy T/R modules. In line with these trends, this thesis presents the design and implementation of the first and only 7-Bit X-Band T/R module with high precision amplitude and phase control in the open literature, which is realized in IHP 0.25μ SiGe BiCMOS technology. In the scope of this thesis, sub-blocks of the designed T/R module such as low noise amplifier (LNA), inter-stage amplifier, SiGe Hetero-Junction Bipolar Transistor (HBT) Single- Pole Double-Throw (SPDT) switch and 7-Bit digitally controlled step attenuator are extensively discussed. The designed LNA exhibits Noise Figure (NF) of 1.7 dB, gain of 23 dB, Output Referred Compression Point (OP1dB) of 16 dBm while the inter-stage amplifier gives measured NF of 3 dB, gain of 15 dB and OP1dB of 18 dBm. Moreover, the designed SPDT switch has an Insertion Loss (IL) of 1.7 dB, isolation of 40 dB and OP1dB of 28 dBm. Lastly, the designed 7-Bit SiGe HBT digitally controlled step attenuator demonstrates IL of 8 dB, RMS attenuation error of 0.18 dB, RMS phase error of 2° and OP1dB of 16 dBm. The 7-Bit T/R module is constructed by using the sub-blocks given above, along with a 7- Bit phase shifter (PS) and a power amplifier (PA). Post-layout simulation results show that the designed T/R module exhibits a gain of 38 dB, RMS phase error of 2.6°, RMS amplitude error of 0.82 dB and Rx-Tx isolation of 80 dB across X-Band. The layout of T/R module occupies an area of 11.37 mm2

Array Architectures and Physical Layer Design for Millimeter-Wave Communications Beyond 5G

Ever increasing demands in mobile data rates have resulted in exploration of millimeter-wave (mmW) frequencies for the next generation (5G) wireless networks. Communications at mmW frequencies is presented with two keys challenges. Firstly, high propagation loss requires base stations (BSs) and user equipment (UEs) to use a large number of antennas and narrow beams to close the link with sufficient received signal power. Consequently, communications using narrow beams create a new challenge in channel estimation and link establishment based on fine angular probing. Current mmW system use analog phased arrays that can probe only one angle at the time which results in high latency during link establishment and channel tracking. It is desirable to design low latency beam training by exploring both physical layer designs and array architectures that could replace current 5G approaches and pave the way to the communications for frequency bands in higher mmW band and sub-THz region where larger antenna arrays and communications bandwidth can be exploited. To this end, we propose a novel signal processing techniques exploiting unique properties of mmW channel, and show both theoretically, in simulation and experiments its advantages over conventional approaches. Secondly, we explore different array architecture design and analyze their trade-offs between spectral efficiency and power consumption and area. For comprehensive comparison, we have developed a methodology for optimal design of system parameters for different array architecture candidates based on the spectral efficiency target, and use these parameters to estimate the array area and power consumption based on the circuits reported in the literature. We show that the hybrid analog and digital architectures have severe scalability concerns in radio frequency signal distribution with increased array size and spatial multiplexing levels, while the fully-digital array architectures have the best performance and power/area trade-offs.The developed approaches are based on a cross-disciplinary research that combines innovation in model based signal processing, machine learning, and radio hardware. This work is the first to apply compressive sensing (CS), a signal processing tool that exploits sparsity of mmW channel model, to accelerate beam training of mmW cellular system. The algorithm is designed to address practical issues including the requirement of cell discovery and synchronization that involves estimation of angular channel together with carrier frequency offset and timing offsets. We have analyzed the algorithm performance in the 5G compliant simulation and showed that an order of magnitude saving is achieved in initial access latency for the desired channel estimation accuracy. Moreover, we are the first to develop and implement a neural network assisted compressive beam alignment to deal with hardware impairments in mmW radios. We have used 60GHz mmW testbed to perform experiments and show that neural networks approach enhances alignment rate compared to CS. To further accelerate beam training, we proposed a novel frequency selective probing beams using the true-time-delay (TTD) analog array architecture. Our approach utilizes different subcarriers to scan different directions, and achieves a single-shot beam alignment, the fastest approach reported to date. Our comprehensive analysis of different array architectures and exploration of emerging architectures enabled us to develop an order of magnitude faster and energy efficient approaches for initial access and channel estimation in mmW systems

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

Amplificadores de potência para radiofrequência insensíveis à impedância de carga

Solid state power amplifiers (SSPAs) evolved significantly over the last few decades, mainly, due to the use of new transistor technologies, such as gallium nitride (GaN) high-electron-mobility transistors (HEMTs), very advanced computer-aided design (CAD) software, and very effective digital pre-distortion (DPD) algorithms. This led to a considerable performance improvement, in terms of energy efficiency, output power, and linearity. To achieve this performance, power amplifier (PA) designers normally push the used transistors very close to their physical safe operating limits, and consider them to operate for a fixed output load. However, the designed PAs are used for many different industrial and/or telecommunication applications, and, in some cases, such as, for example, microwave cooking or massive multiple-input multiple-output (MIMO) fifth generation (5G) base stations (BSs), the output load of these amplifiers can change. Under this nonoptimal scenario, the used transistors will operate for non-nominal loads, and the PAs performance can be severely degraded. Moreover, in highly optimized designs, where the transistors are operated close to their safe limits, their reliability can be reduced or, in extreme cases, they can even be permanently damaged. Therefore, load insensitive PA architectures, and/or techniques that aim at reducing the load variation seen by the PA, are necessary to improve the performance under load varying scenarios. This thesis presents various strategies to improve load insensitiveness of PAs. The presented techniques are based on tunable matching networks (TMNs) and on the amplifiers’ drain supply voltage (VDS) variation. The developed TMNs successfully reduced the load variation seen by the PA, and its performance was greatly improved, for non-optimal loading, by also using the derived load dependent VDS variation. These different approaches were tested and validated on single-ended PAs and then, based on their advantages and disadvantages, the most promising technique – the supply voltage modulation – was selected for the design of a Doherty power amplifier (DPA), which is of paramount importance for telecommunication applications. Moreover, since in some applications the output load variation can be unpredictable, we also developed a complete quasi-load insensitive (QLI) PA system that includes an impedance tracking circuit and an automatic real-time compensation of the amplifier performance.Os amplificadores de potência de estado sólido (SSPAs) evoluíram significativamente nas últimas décadas, principalmente devido à utilização de novas tecnologias de transístores, como os transístores de alta mobilidade (HEMTs) de nitreto de gálio (GaN), de ferramentas muito avançadas de projeto assistido por computador (CAD) e de algoritmos de pré-distorção digital (DPD) muito evoluídos. Isto levou a uma melhoria de desempenho considerável, em termos de eficiência energética, potência de saída e linearidade. Normalmente, para obter estes níveis de desempenho, os engenheiros projetam os amplificadores permitindo que os transístores utilizados operem muito perto do seu limite físico de funcionamento seguro e considerando que vão operar para uma carga fixa. No entanto, os amplificadores projetados são utilizados em diversas aplicações industriais e/ou telecomunicações e, em alguns casos, como por exemplo fornos micro-ondas ou estações base 5G, a sua carga de saída pode variar devido a várias causas, que podem ser previsíveis ou imprevisíveis. Neste cenário não ideal, os transístores utilizados operam para cargas não ótimas e o desempenho dos amplificadores pode ser muito degradado. Além disso, em projetos muito otimizados, onde os transístores são operados perto do seu limite de funcionamento seguro, a sua durabilidade pode ser reduzida ou, em casos extremos, podem até ser permanentemente danificados. Portanto, para melhorar o desempenho dos amplificadores em cenários de carga variável, são necessárias novas arquiteturas e/ou técnicas que visam reduzir a variação da carga vista pelos transístores utilizados. Esta tese apresenta várias estratégias para melhorar a insensibilidade dos amplificadores em relação à variação de carga. As técnicas apresentadas são baseadas em malhas de adaptação dinâmicas (TMNs) e na variação da tensão de alimentação dos amplificadores. As malhas de adaptação desenvolvidas permitiram reduzir a variação de carga vista pelo amplificador e a variação da sua tensão de alimentação permitiu melhorar o desempenho para operação com cargas não ótimas. Estas abordagens foram testadas e validadas em amplificadores baseados num só transístor, e, posteriormente, com base nas suas vantagens e desvantagens, a técnica mais promissora – a modulação da tensão de alimentação – foi selecionada para o projeto de um amplificador Doherty, que é imprescindível para telecomunicações. Além disso, como em algumas aplicações a variação da carga de saída pode ser imprevisível, também desenvolvemos um sistema completo que inclui um circuito de medida de impedância e compensação do desempenho do amplificador em tempo real.Programa Doutoral em Engenharia Eletrotécnic

Integrated Optical Delay Line Circuits on a Ultra-low Loss Planar Waveguide Platform

Photonic integrated circuits (PICs) play a major role in the advancement of optical networks. One of the constraints of PICs is the high propagation loss of optical waveguides. As the complexity in PICs increases, so does the power usage and heat generation; therefore, bringing “fiber-like” losses on-chip would not only allow for the improvement of chip performance, but it would also revolutionize delay line technologies allowing longer delay lines to be integrated on chip, otherwise not practically feasible. The design of such waveguides and optical circuits requires a balance of numerous tradeoffs between mode-size, bending radius, and footprint, to name a few. Herein, we present the design and fabrication of optical delay line circuits using an ultra-low loss waveguide platform, which utilizes a high aspect ratio buried Si3N4 core planar waveguide. Optical delay line circuits are defined here as any optical circuit that requires the optical signal to be delay by a certain amount of time for its proper functionality. Such devices are used in many applications ranging from medical to sensing and national defense. In this dissertation we present the integration of three optical delay line circuits: Tunable true time delay for broadband phased array antennas application, a programmable dispersion compensation filter, and an optical gyroscope waveguide coil. The design tradeoff, fabrication, and results for each circuit are present and highlighted in detail