고속 시리얼 링크를 위한 고리 발진기를 기반으로 하는 주파수 합성기

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links. To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power. As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.본 논문은 현대 시리얼 링크의 클락킹에 관여되는 주요한 문제들에 대하여 기술한다. 준속도, 다중 표준 구조들이 채택되고 있는 추세에 따라, 기존의 클라킹 방법은 낮은 비용의 구현의 관점에서 새로운 혁신을 필요로 한다. LC 공진기를 대신하여 능동 소자 발진기를 사용한 주파수 합성에 대하여 알아보고, 이에 발생하는 두가지 주요 문제점과 각각에 대한 해결 방안을 탐색한다. 각 제안 방법을 프로토타입 칩을 통해 그 효용성을 검증하고, 이어서 능동 소자 발진기가 미래의 고속 시리얼 링크의 클락킹에 사용될 가능성에 대해 검토한다. 첫번째 시연으로써, 고주파 고리 발진기의 높은 플리커 잡음을 완화시키기 위해 기준 신호를 배수화하여 뒷단의 위상 고정 루프의 대역폭을 효과적으로 극대화 시키는 회로 기술을 제안한다. 본 기술은 지터를 누적 시키지 않으며 따라서 깨끗한 중간 주파수 클락을 생성시켜 위상 고정 루프와 함께 높은 성능의 고주파 클락을 합성한다. 기준 신호를 성공적으로 배수화하기 위한 타이밍 조건들을 먼저 분석하여 타이밍 오류를 제거하기 위한 방법론을 파악한다. 각 교정 중량은 연역적 확률을 기반으로한 LMS 알고리즘을 통해 갱신되도록 설계된다. 교정에 필요한 시간을 최소화 하기 위하여, 각 교정 이득은 타이밍 오류 근원들의 크기를 귀납적으로 추론한 값을 바탕으로 지속적으로 제어된다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 저소음, 고주파 클락을 빠른 교정 시간안에 합성해 냄을 확인하였다. 이는 177/223 fs의 rms 지터를 가지는 8/16 GHz의 클락을 출력한다. 두번째 시연으로써, 고리 발진기의 높은 전원 노이즈 의존성을 완화시키는 기술이 포함된 주파수 합성기가 설계되었다. 이는 고리 발진기의 전압 헤드룸을 보존함으로서 고주파 발진을 가능하게 한다. 나아가, 전원 노이즈 감소 성능은 공정, 전압, 온도 변동에 대하여 민감하지 않으며, 따라서 추가적인 교정 회로를 필요로 하지 않는다. 마지막으로, 위상 노이즈에 대한 포괄적 분석과 회로 최적화를 통하여 주파수 합성기의 저잡음 출력을 방해하지 않는 방법을 고안하였다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 전원 노이즈가 인가되지 않은 상태에서 289 fs의 rms 지터를 가지는 8 GHz의 클락을 출력한다. 또한, 20 mVrms의 전원 노이즈가 인가되었을 때에 유도되는 지터의 양을 -23.8 dB 만큼 줄이는 것을 확인하였다.1 Introduction 1 1.1 Motivation 3 1.1.1 Clocking in High-Speed Serial Links 4 1.1.2 Multi-Phase, High-Frequency Clock Conversion 8 1.2 Dissertation Objectives 10 2 RO-Based High-Frequency Synthesis 12 2.1 Phase-Locked Loop Fundamentals 12 2.2 Toward All-Digital Regime 15 2.3 RO Design Challenges 21 2.3.1 Oscillator Phase Noise 21 2.3.2 Challenge 1: High Flicker Noise 23 2.3.3 Challenge 2: High Supply Noise Sensitivity 26 3 Filtering RO Noise 28 3.1 Introduction 28 3.2 Proposed Reference Octupler 34 3.2.1 Delay Constraint 34 3.2.2 Phase Error Calibration 38 3.2.3 Circuit Implementation 51 3.3 IL-ADPLL Implementation 55 3.4 Measurement Results 59 3.5 Summary 63 4 RO Supply Noise Compensation 69 4.1 Introduction 69 4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72 4.2.1 Circuit Implementation 73 4.2.2 Frequency-Domain Analysis 76 4.2.3 Circuit Optimization 81 4.3 ADPLL Implementation 87 4.4 Measurement Results 90 4.5 Summary 98 5 Conclusions 99 A Notes on the 8REF 102 B Notes on the ACSC 105박

Switched Capacitor Loop Filter 와 Source Switched Charge Pump 를 이용한 Phase-Locked Loop 의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.본 논문에서는 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 가지며 스위치축전기 루프 필터와 소스 스위치 전하 펌프를 이용한 PLL 을 제안한다. 제안된 PLL 은 레퍼런스 스퍼의 성능을 위해 넓은 컨트롤 전압의 범위 동안 전류의 오차를 줄여주고 전하 공유 효과를 줄여주는 하나의 조절 가능한 전하 펌프를 사용하였다. 저항의 온도, 공급 전압, 공정 변화에 따른 민감도를 낮추기 위해 스위치 축전기 루프 필터가 사용되었다. 다양한 인터페이스 표준을 지원하기 위해 제안하는 PLL 은 넓은 주파수 범위를 지원하고 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 갖는다. 스위치 축전기 루프 필터와 소스 스위치 전하 펌프의 동작 원리에 대해 분석하였다. 40 nm CMOS 공정으로 제작되었으며, 제안된 회로는 quarter-rate 송신기를 위해 4 개의 phase 를 만들어내며 750 MHz 의 레퍼런스 클락을 이용하여 12 GHz 에서 6.35 mW 의 power 를 소모하고 0.008mm2 의 유효 면적을 차지하고 10 kHz 부터 100 MHz 까지 적분했을 때의 RMS jitter 값은 244.8fs 이다. 제안하는 PLL 은 -244.2 dB 의 FoM, 0.53 mW/GHz 의 power 효율을 달성했으며 레퍼런스 스퍼는 -60.3 dBc 이다CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUNDS 4 2.1 CLOCK GENERATION IN SERIAL LINK 4 2.2 PLL BUILDING BLOCKS 6 2.2.1 OVERVIEW 6 2.2.2 PHASE FREQUENCY DETECTOR 7 2.2.3 CHARGE PUMP AND LOOP FILTER 9 2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10 2.2.5 FREQUENCY DIVIDER 13 2.3 PLL LOOP ANALYSIS 15 CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19 3.1 DESIGN CONSIDERATION 19 3.2 PROPOSED ARCHITECTURE 21 3.3 CIRCUIT IMPLEMENTATION 23 3.3.1 PHASE FREQUENCY DETECTOR 23 3.3.2 SOURCE SWITCHED CHARGE PUMP 26 3.3.3 SWITCHED CAPACITOR LOOP FILTER 30 3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35 3.3.5 POST VCO AMPLIFIER 39 3.3.6 FREQUENCY DIVIDER 40 CHAPTER 4 MEASUREMENT RESULTS 43 4.1 CHIP PHOTOMICROGRAPH 43 4.2 MEASUREMENT SETUP 45 4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47 4.4 PERFORMANCE SUMMARY 50 CHAPTER 5 CONCLUSION 52 BIBLIOGRAPHY 53 초 록 58석

LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos

Inductorless Frequency Synthesizers for Low-Cost Wireless

AbstractThe quest for ubiquitous wireless connectivity, drives an increasing demand for compact and efficient means of frequency generation. Conventional synthesizer options, however, generally trade one requirement for the other, achieving either excellent levels of efficiency by leveraging LC-oscillators, or a very compact area by relying on ring-oscillators. This chapter describes a recently introduced class of inductorless frequency synthesizers, based on the periodic realignment of a ring-oscillator, that have the potential to break this tradeoff. After analyzing their jitter-power product, the conditions that ensure optimum performance are derived and a novel digital-to-time converter range-reduction technique is introduced, to enable low-jitter and low-power fractional-N frequency synthesis. A prototype, which implements the proposed design guidelines and techniques, has been fabricated in 65 nm CMOS. It occupies a core area of 0:0275 mm$$^{2}$$ 2 and covers the 1:6-to-3:0 GHz range, achieving an absolute rms jitter (integrated from 30 kHz-to-30 MHz) of 397 fs at 2:5 mW power. With a corresponding jitter-power figure-of-merit of −244 dB in the fractional-N mode, the prototype outperforms prior state-of-the-art inductorless frequency synthesizers

Digital controlled oscillator (DCO) for all digital phase-locked loop (ADPLL) – a review

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL

Ring oscillator based injection locked clock multiplier

This thesis describes a ring-based injection locked clock multiplier (ILCM) designed with the goal of generating a high-frequency and low-jitter clock. Building on prior research done on injection locking, this design uses a reference frequency doubling technique to push the noise bandwidth of the circuit to Fref/3 to suppress DCO noise to a large extent. A background duty cycle error correction technique is employed to correct errors on the doubled clock that could be detrimental to performance. The design also modifies an existing architecture to achieve type-II suppression of DCO noise in order to fully suppress the flicker noise which becomes prevalent in low process nodes. The prototype ILCM was fabricated in TSMC 65 nm CMOS technology. Thorough testing was performed to characterize the effectiveness of the aforementioned techniques. The circuit achieves 340 fsrms integrated jitter when operating at 5 GHz while only consuming 5.3 mW of power. The ILCM's figure of merit, -242.4 dB, is on par with state-of-the-art ring-based clock multipliers while operating at a much higher output frequency and multiplication factor than previously published work. These results indicate the effectiveness of reference frequency doubling in a ring-based, high-performance clock multiplier design

Self-Calibrated, Low-Jitter and Low-Reference-Spur Injection-Locked Clock Multipliers

Department of Electrical EngineeringThis dissertation focuses primarily on the design of calibrators for the injection-locked clock multiplier (ILCM). ILCMs have advantage to achieve an excellent jitter performance at low cost, in terms of area and power consumption. The wide loop bandwidth (BW) of the injection technique could reject the noise of voltage-controlled oscillator (VCO), making it thus suitable for the rejection of poor noise of a ring-VCO and a high frequency LC-VCO. However, it is difficult to use without calibrators because of its sensitiveness in process-voltage-temperature (PVT) variations. In Chapter 2, conventional frequency calibrators are introduced and discussed. This dissertation introduces two types of calibrators for low-power high-frequency LC-VCO-based ILFMs in Chapter 3 and Chapter 4 and high-performance ring-VCO-based ILCM in Chapter 5. First, Chapter 3 presents a low power and compact area LC-tank-based frequency multiplier. In the proposed architecture, the input signals have a pulsed waveform that involves many high-order harmonics. Using an LC-tank that amplifies only the target harmonic component, while suppressing others, the output signal at the target frequency can be obtained. Since the core current flows for a very short duration, due to the pulsed input signals, the average power consumption can be dramatically reduced. Effective removal of spurious tones due to the damping of the signal is achieved using a limiting amplifier. In this work, a prototype frequency tripler using the proposed architecture was designed in a 65 nm CMOS process. The power consumption was 950 ??W, and the active area was 0.08 mm2. At a 3.12 GHz frequency, the phase noise degradation with respect to the theoretical bound was less than 0.5 dB. Second, Chapter 4 presents an ultra-low-phase-noise ILFM for millimeter wave (mm-wave) fifth-generation (5G) transceivers. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600??W to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was ???129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were???39.1 dBc and 86 fs, respectively. Third, Chapter 5 presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based ILCM. Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the three root causes of the frequency errors of ILCMs (i.e., frequency drift, phase offset, and slope modulation), the ILCM of this work is able to achieve a low-level reference spur. In addition, the calibrating loop for the frequency drift of the TP-FPSC offers an additional suppression to the in-band phase noise of the output signal. This capability of the TP-FPSC and the naturally wide bandwidth of the injection-locking mechanism allows the ILCM to achieve a very low RMS jitter. The ILCM was fabricated in a 65-nm CMOS technology. The measured reference spur and RMS jitter were ???72 dBc and 140 fs, respectively, both of which are the best among the state-of-the-art ILCMs. The active silicon area was 0.055 mm2, and the power consumption was 11.0 mW.clos

Techniques for low jitter clock multiplication

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 115-121).Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to path mismatch in the detector as well as analog nonidealities in the tuning circuits. This thesis proposes a mostly-digital tuning technique that drastically reduces deterministic jitter in phase realigning clock multipliers. The proposed technique eliminates path mismatch by using a single-path digital detection method that leverages a scrambling time-to-digital converter (TDC) and correlated double sampling to infer the tuning error from the difference in cycle periods of the output. By using a digital loop filter that consists of a digital accumulator, the tuning technique avoids the analog nonidealities of typical tuning paths. The scrambling TDC is not a contribution of this thesis. A highly-digital MDLL prototype that uses the proposed tuning technique consists of two custom 0.13 [mu]m ICs, an FPGA board, a discrete digital-to-analog converter (DAC) with effective 8 bits, and a simple RC filter. The measured performance (for a 1.6 GHz output and 50 MHz reference) demonstrated an overall jitter of 0.93 ps rms, and estimated random and deterministic jitter of 0.68 ps rms and 0.76 ps peak-to-peak, respectively. The proposed MDLL architecture is especially suitable for digital ICs, since its highly-digital architecture is mostly compatible with digital design flows, which eases its porting between technologies.by Belal Moheedin Helal.Ph.D

Clock multiplication techniques for high-speed I/Os

Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored. First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz. Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB. Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively

Techniques for Frequency Synthesizer-Based Transmitters.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd