Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

E-link: A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication

The e-link, an electrical interface suitable for transmission of data over PCBs or electrical cables, within a distance of a few meters, at data rates up to 320 Mbit/s, is presented. The elink is targeted for the connection between the GigaBit Transceiver (GBTX) chip and the Front-End (FE) integrated circuits. A commercial component complying with the Scalable Low- Voltage Signaling (SLVS) electrical standard was tested and demonstrated a performance level compatible with our application. Test results are presented. A SLVS transmitter/receiver IP block was designed in 130 nm CMOS technology. A test chip was submitted for fabrication

Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

전원 잡음에 둔감한 고리 발진기와 디지털 위상 동기 회로 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.One of the critical blocks integrated into the PAM4-binary bridge, bridging the high-speed DRAM and the low-speed DRAM Tester, is an All-Digital Phase-Locked Loop (ADPLL). Since the transmitter and receiver operate based on the clock signal, whose frequency is doubled compared to the clock signal transmitted from the memory tester by the ADPLL, the ADPLL needs to have a low RMS jitter and high Process-Voltage-Temperature (PVT) tolerance characteristics. However, due to the complex bridge circuit sharing the supply power with the ADPLL, power supply noise (PSN) is the main challenge for the Ring Oscillator (RO) based ADPLL. This thesis presents a Supply Noise-Insensitive RO-based ADPLL. A supply noise absorbing shunt regulator composed of 31-bit NMOS transistors Array is embedded parallel to the RO. Output codes from the Digital Loop Filter (DLF) not only control the Digitally-Controlled Resistor (DCR) but also the transconductance of the NMOS transistor Array. The proposed ADPLL is fabricated in the 40-nm CMOS technology. The ADPLL occupies an active area of 0.06 mm2 and consumes power 13.5 mW, while the proposed scheme only takes 6.6% and 2.8% of it, respectively. At 8 GHz operation, the proposed ADPLL achieves an RMS jitter of 3.255 ps with 1-MHz 40-mVpp sinusoidal noise injected into the supply voltage. With the Supply Noise-Insensitive technique, the RMS jitter lowers to 1.268 ps.고속 DRAM과 저속 검사 장비를 연결하는 4단계 펄스 진폭 변조-2진법 브리지 칩의 주요 구성 회로 중에 디지털 위상 동기 회로가 있다. 이 회로가 검사 장비에서 온 참조 클락의 진동수를 2배로 빠르게 하여 출력하고, 그 클락을 기준으로 칩의 송수신 회로들이 동작하기 때문에 낮은 RMS 지터와 공정-전압-온도 변화에 둔감한 성능이 요구된다. 하지만, 칩의 복잡한 회로들 때문에 고리 발진기를 기반으로 한 이 회로에게 전원 전압 잡음이 가장 큰 문제점이 된다. 본 논문은 전원 잡음에 둔감한 고리 발진기를 기반으로 한 디지털 위상 동기 회로를 제안한다. 전원 잡음을 흡수하는 단락 레귤레이터 역할의 31-비트NMOS 트랜지스터 배열이 고리 발진기와 평행하게 구현되었다. 디지털 제어 저항을 조절하는 디지털 루프 필터에서 온 행 조정 비트들이 NMOS 트랜지스터 배열의 트랜스컨덕턴스도 조절하게 디자인하였다. 제안된 디지털 위상 동기 회로는 40-nm CMOS 공정으로 제작되었다. 0.06 mm2 의 면적을 차지하고 13.5 mW의 전력을 소모하며, 고안된 전원 잡음 흡수 회로는 각각 0.0017 mm2와 0.9mW, 즉, 전체의 6.6%와 2.8%만 차지하였다. 8GHz 동작에서, 제안된 회로는 1-MHz 40-mVpp 사인파 전원 잡음 아래에서 3.255 ps의 RMS 지터를 보였지만, 고안된 회로의 동작과 함께 1.268 ps로 줄었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 OVERVIEW 5 2.2 COMPOSITIONS OF THE ADPLL 8 2.2.1 TIME-TO-DIGITAL CONVERTER 8 2.2.2 DIGITAL LOOP FILTER 11 2.2.3 DIGITALLY CONTROLLED OSCILLATOR 14 2.2.4 PRIOR WORKS OF SUPPLY NOISE CANCELLATION 19 2.3 ADPLL LOOP ANALYSIS 21 2.3.1 LOOP TRANSFER FUNCTION 21 2.3.2 NOISE MODELING 23 CHAPTER 3 DESIGN OF SUPPLY NOISE-INSENSITIVE ADPLL 26 3.1 DESIGN CONSIDERATION 26 3.2 OVERALL ARCHITECTURE 28 3.3 PROPOSED CIRCUIT IMPLEMENTATION 30 3.3.1 PFD-TDC AND DIGITAL BLOCK 30 3.3.2 PROPOSED DCO WITH DCR 33 3.3.3 NMOS SHUNT REGULATOR ARRAY 37 3.3.4 SUPPLY SENSING AMPLIFIER 39 3.3.5 SUPPLY NOISE-INSENSITIVE TECHNIQUE 41 CHAPTER 4 MEASUREMENT RESULTS 43 4.1 CHIP PHOTOMICROGRAPH 43 4.2 MEASUREMENT SETUP 45 4.3 MEASUREMENT RESULTS 46 4.3.1 FREE-RUNNING DCO 46 4.3.2 CLOSED-LOOP PERFORMANCE 47 4.4 PERFORMANCE SUMMARY 49 CHAPTER 5 CONCLUSION 51 BIBLIOGRAPHY 52 초 록 55석

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

Optical Data Transmission ASICs for the High-Luminosity LHC (HL-LHC) Experiments

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments.Comment: 9 pages, 12 figure