The e-link, an electrical interface suitable for transmission of data over PCBs or electrical cables, within a distance of a few meters, at data rates up to 320 Mbit/s, is presented. The elink is targeted for the connection between the GigaBit Transceiver (GBTX) chip and the Front-End (FE) integrated circuits. A commercial component complying with the Scalable Low- Voltage Signaling (SLVS) electrical standard was tested and demonstrated a performance level compatible with our application. Test results are presented. A SLVS transmitter/receiver IP block was designed in 130 nm CMOS technology. A test chip was submitted for fabrication

Bonacini, S

Kloukinas, K

Moreira, P

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e-link: A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip CommunicationS. Bonacinia, K. Kloukinasa, P. MoreiraaaCERN, 1211 Geneva 23, Switzerlandsandro.bonacini@cern.chAbstractThe e-link, an electrical interface suitable for transmission ofdata over PCBs or electrical cables, within a distance of a fewmeters, at data rates up to 320 Mbit/s, is presented. The e-link is targeted for the connection between the GigaBit Trans-ceiver (GBTX) chip and the Front-End (FE) integrated circuits.A commercial component complying with the Scalable Low-Voltage Signaling (SLVS) electrical standard was tested anddemonstrated a performance level compatible with our applica-tion. Test results are presented. A SLVS transmitter/receiver IPblock was designed in 130 nm CMOS technology. A test chipwas submitted for fabrication.I. INTRODUCTIONWith the future upgrade of the LHC and its associated exper-iments the number of tracker detector channels will increase byone order of magnitude with respect to the LHC trackers justcompleted. Nonetheless, the design strives to reduce the to-tal material inside the detectors, which is mainly due to cables,cooling and mechanical support, the last one being related to theother two. It is thus necessary to minimize the power consump-tion of the electronic devices in the front-end (FE) and the num-ber of cables required. This can be achieved by new low-powerinterconnection schemes between the FE and the off-detectorelectronics, and among the on detector Application-Specific In-tegrated Circuits (ASICs); numerous slow data links could beaggregated into fewer faster and more efficient links.The use of an advanced CMOS technology, which allowsseveral supply voltage levels for different purpouses, helps theminimization of power of the FE’s ASICs.The recent technology advancements demonstrated seriallinks as fast as 10 Gbps and above implemented in 130 nmCMOS technology. The GBT project was started to design thefuture optical data link for the experiments, which brings to-gether the functions of data readout, trigger and control. TheGBT will be connected to a number of up to 32 FE ASICs, re-quiring each one a dedicated electrical link, in a star-point topol-ogy. These links target short distance transmission (typically upto 2 meters on PCB, and up to 4 meters on cable) and shall beas much as possible insensitive to common-mode voltage varia-tions.The front-end electronics of particle physics detectors aimto achieve high levels of performance in terms of resolution andaccuracy. This performance is limited by the system intrinsicnoise, therefore electrical links should be designed to minimizecrosstalk and power supply noise.For these reasons, the study of a low-power low-voltage-swing electrical link was carried out. Among the several linkexamined, the Scalable Low-Voltage Signaling (SLVS) indus-try standard was chosen and tested. The protocol is briefly de-scribed in section II. The tests are described in section III.Since the link circuitry shall be placed in the FE, it needsto work properly in the harsh environment of the experimentscharacterized by high level of radiation (up to hundreds of Mrd)and intense magnetic field (up to 4T). These constraints makecommercial components not suitable and require the design ofnovel radiation-hard trasmitter and receiver circuits.The design of an SLVS transmitter and an SLVS receiverwas carried out, as part of the GBT project, for the interconnec-tion between the GBTX chip and the FE ASICs. The design ispresented in section IV.II. THE SLVS STANDARDThe SLVS standard is defined in [1] and describes a differen-tial current-steering electrical protocol with a voltage swing of200 mV on a 100 Ω load and a common mode of 200 mV. Thedifferential voltage is therefore 400 mV as depicted in Fig. 1.Figure 1: SLVS standard signaling scheme.The output current is 2 mA, with a power consumption at theload of 0.4 mW. The reduction in common-mode with respect toother standards, like LVDS, allows the use of a supply voltageas low as 0.8 V for the output driver circuitry.A few commercial parts which comply to this standard areavailable, mainly from National Semiconductors, and their tar-get application is in mobile/portable devices as short (< 30 cm)communication links over PCB traces and flat cable.III. BIT ERROR RATE TESTINGThe test aimed to demonstrate the capability of the electricalprotocol to work with longer distances and different media than422the parts normal application.A. Test setupA commercial part which uses the SLVS standard was testedwith several media types and lengths (5 m Ethernet cable, 24 cmkapton, 2 m PCB and others) at two different speeds (320 Mbpsand 480 Mbps). The part we used is the LM4308 from NationalSemiconductors.The test setup is composed of- two Xilinx Spartan-3E evaluation boards,- two custom PCBs holding each two LM4308 components,- two link media,arranged like in Fig. 2.Xilinx S3EboardXilinx S3EboardLM4308 media LM4308LM4308mediaLM4308181818182222Figure 2: Test setup (clock signals are not shown).Figure 3: Test setup picture.The LM4308 chip is an SLVS serdes, which can behardwire-configured to be either a serializer or a deserializer. Inthe test, two LM4308 chips are serializers while the other twoare deserializers.Each one of the Xilinx Spartan-3E chips generates a pseudo-random sequence, which is fed to a serializer chip, and checksthe sequence coming from a deserializer chip. The link mediaare connected to the serdes boards through Samtec QTE/QSEconnectors.A few special PCB-type media were fabricated for this pur-pouse: a 1-m microstrip, a 2-m microstrip and a 2-m stripline;these lines follow a serpentine path to minimize area. An Eth-ernet plug adapter was also fabricated in order to test Ethernetcables.B. Test resultsThe test results are described in Table 1. The eye-diagramin Fig 4 has been obtained at 480 Mbps at the load of a 2-mmicrostrip PCB line.It should be noted that the LM4308 uses a forwarded-clocktechnique, therefore the bit errors which were measured mightas well come from the clock line, which in all media runs alongthe data line.Table 1: SLVS test resultsMedia 320 Mbps 480 Mbps1-m microstrip < 1 · 10−13 < 1 · 10−132-m microstrip < 1 · 10−13 < 1 · 10−132-m stripline < 1 · 10−13 < 1 · 10−1324-cm Kapton < 3 · 10−14 < 1 · 10−135-m ethernet cable < 1 · 10−13 2 · 10−11Figure 4: Eye diagram at load, at 480 Mbps using a 2-m microstripboard medium.The test results of the SLVS standard were encouraging anddemonstrated performance compatible with our target applica-tionsIV. SLVS TRANSMITTER AND RECEIVER IPBLOCKS DESIGNA transmitter and receiver IP blocks for integration in the FEASICs, complying with the SLVS protocol, were designed in a130 nm technology. The e-link can operate at any speed up to320 Mbps. The transmitter and receiver blocks are designed tobe rad-hard and SEU-hard.Though these IP blocks are targeted for the implementationof the GBTX-FE connection, they are also suitable for generalchip-to-chip communication within the LHC experiments.The transmitter and receiver circuits are designed to be pow-ered in the range from 1.0 to 1.5 V.Studies on the radiation tolerance of the technology used [3]suggest that thin-oxide transistors suffer limited total dose ef-fects. Only thin-oxide transistors are used in the design, avoid-ing any special layout technique. SEU-robustness is assured bytriplicating all low-capacitance nodes and logic elements.423Tx+ Tx-Vref,cmVbias,cmVbias,ipredrv+predrv-Vcm1kΩ1kΩx20x20x20x20x20x20Zero-VtZero-VtZero-VtIref+–Output stageReplica bias for common-mode setCurrent output setM2M1cset[3:0]Figure 5: Transmitter output stage schematic.VbiasIn-In+VbiasVbiasVbiasVbiasVbiasVbiasOutFigure 6: Receiver first stage schematic.A. TransmitterThe transmitter, whose schematic is shown in Fig. 5, is im-plemented by a N-over-N driver which steers the current givenby the current source M1. The common-mode is kept at Vref,cm= 200 mV by the replica bias of the source-follower M2.In order to minimize the power consumption, the currentoutput is adjustable from 2 mA down to 0.5 mA, with a 60%power reduction and thus proportional lowering of crosstalk.The transmitter can also be set into a power-down state whenunused. The current output is set by a 4-bit digital switch (notin the figure).In power-down mode, all the biasing circuits are switchedoff and the pre-driver stops toggling the final stage. The trans-mitter consumes 3 mW at 320 Mbps, with 1.2 V supply voltageand 2 mA output.B. ReceiverThe receiver is implemented by a rail-to-rail differential am-plifier, shown in Fig. 6, such that it guarantees a wide common-mode voltage range. The receiver can be as well set into apower-down state when unused.The first stage amplifier, similar to [2], is a combination oftwo basic complementary amplifiers, which together can coverfully the input range from negative to positive supply. More-over, the amplifier is self-biased through a negative feedbackmechanism.In power-down mode the biasing is switched off, which pre-vents toggling on the output. The receiver consumes 210 µW at320 Mbps, 1.2 V supply and with a 64 fF output load.424C. Test chipA test chip containing the SLVS receiver and the SLVStransmitter was designed and submitted for fabrication. Thetest chip works as an LVDS-to-SLVS translator and viceversa.A few CMOS input pins are present to control the transmittercurrent output setting and the receiver shutdown. A loopbackcontrol pin is also provided for testing.Figure 7: Test chip layout.Testing will be performed on the chip to evaluate the bit errorrate in the same fashion as the commercial part.V. CONCLUSIONSThe SLVS electrical standard for the e-link, targeted forthe connection between the GBTX chip and the FE ASICs,was tested with a commercial part and demonstrated a perfor-mance level compatible with our application. An SLVS trans-mitter/receiver IP block was designed in 130 nm CMOS tech-nology and the test chip was submitted for fabrication.Future improvements might include the implementation ofprogrammable pre-emphasis in the transmitter and investigateLVDS compatibility of the electrical levels.REFERENCES[1] JEDEC, JESD8-13, Scalable Low-Voltage Signaling for400 mV (SLVS-400).[2] M. Bazes, Two Novel Fully Complementary Self-BiasedCMOSDifferential Amplifiers, IEEE Journal of Solid-StateCircuits, Vol. 26, No. 2, Feb. 1991.[3] F. Faccio & G. Cervelli.Radiation-induced edge effects indeep submicron CMOS. transistors. IEEE Transactions onNuclear Science, vol. 52, no. 6, pages 2413–2420, Decem-ber 2005.425

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