A Servo-Clock Model for Chains of Transparent Clocks Affected by Synchronization Period Jitter

n/

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

Circuit design and analysis for on-FPGA communication systems

On-chip communication system has emerged as a prominently important subject in Very-Large- Scale-Integration (VLSI) design, as the trend of technology scaling favours logics more than interconnects. Interconnects often dictates the system performance, and, therefore, research for new methodologies and system architectures that deliver high-performance communication services across the chip is mandatory. The interconnect challenge is exacerbated in Field-Programmable Gate Array (FPGA), as a type of ASIC where the hardware can be programmed post-fabrication. Communication across an FPGA will be deteriorating as a result of interconnect scaling. The programmable fabrics, switches and the specific routing architecture also introduce additional latency and bandwidth degradation further hindering intra-chip communication performance. Past research efforts mainly focused on optimizing logic elements and functional units in FPGAs. Communication with programmable interconnect received little attention and is inadequately understood. This thesis is among the first to research on-chip communication systems that are built on top of programmable fabrics and proposes methodologies to maximize the interconnect throughput performance. There are three major contributions in this thesis: (i) an analysis of on-chip interconnect fringing, which degrades the bandwidth of communication channels due to routing congestions in reconfigurable architectures; (ii) a new analogue wave signalling scheme that significantly improves the interconnect throughput by exploiting the fundamental electrical characteristics of the reconfigurable interconnect structures. This new scheme can potentially mitigate the interconnect scaling challenges. (iii) a novel Dynamic Programming (DP)-network to provide adaptive routing in network-on-chip (NoC) systems. The DP-network architecture performs runtime optimization for route planning and dynamic routing which, effectively utilizes the in-silicon bandwidth. This thesis explores a new horizon in reconfigurable system design, in which new methodologies and concepts are proposed to enhance the on-FPGA communication throughput performance that is of vital importance in new technology processes

Using quantum key distribution for cryptographic purposes: a survey

The appealing feature of quantum key distribution (QKD), from a cryptographic viewpoint, is the ability to prove the information-theoretic security (ITS) of the established keys. As a key establishment primitive, QKD however does not provide a standalone security service in its own: the secret keys established by QKD are in general then used by a subsequent cryptographic applications for which the requirements, the context of use and the security properties can vary. It is therefore important, in the perspective of integrating QKD in security infrastructures, to analyze how QKD can be combined with other cryptographic primitives. The purpose of this survey article, which is mostly centered on European research results, is to contribute to such an analysis. We first review and compare the properties of the existing key establishment techniques, QKD being one of them. We then study more specifically two generic scenarios related to the practical use of QKD in cryptographic infrastructures: 1) using QKD as a key renewal technique for a symmetric cipher over a point-to-point link; 2) using QKD in a network containing many users with the objective of offering any-to-any key establishment service. We discuss the constraints as well as the potential interest of using QKD in these contexts. We finally give an overview of challenges relative to the development of QKD technology that also constitute potential avenues for cryptographic research.Comment: Revised version of the SECOQC White Paper. Published in the special issue on QKD of TCS, Theoretical Computer Science (2014), pp. 62-8

Probabilistic analysis of defect tolerance in asynchronous nano crossbar architecture

Among recent advancements in technology, nanotechnology is particularly promising. Most researchers have begun to focus their efforts on developing nano scale circuits. Nano scale devices such as carbon nano tubes (CNT) and silicon nano wires (SiNW) form the primitive building blocks of many nano scale logic devices and recently developed computing architecture. One of the most promising nanotechnologies is crossbar-based architecture, a two-dimensional nanoarray, formed by the intersection of two orthogonal sets of parallel and uniformly-spaced CNTs or SiNWs. Nanowire crossbars offer the potential for ultra-high density, which has never been achieved by photolithography. In an effort to improve these circuits, our research group proposed a new Null Convention Logic (NCL) based clock-less crossbar architecture. By eliminating the clock, this architecture makes possible a still higher density in reconfigurable systems. Defect density, however, is directly proportional to the density of nanowires in the architecture. Future work, therefore, must improve the defect tolerance of these asynchronous structures. The thesis comprises two papers. The first introduces asynchronous crossbar architecture and concludes with the validation of mapping a 1-bit adder on it. It also discusses various advantages of asynchronous crossbar architecture over clock based nano structures. The second paper concentrates on the probabilistic analysis of asynchronous nano crossbar architecture to address the high defect rates in these structures. It analyzes the probability distribution of mapping functions over the structure for varying number of defects and proposes a method to increase the probability of successful mapping --Abstract, page iv

DoA and ToA Estimation, Device Positioning and Network Synchronization in 5G New Radio : Algorithms and Performance Analysis

Location information plays a significant role not only in our everyday life through various location-based services, but also in emerging technologies such as virtual reality, robotics, and autonomous driving. In contrast to the existing and earlier cellular generations, positioning has been considered as a key element in future cellular networks from the very beginning of the fifth generation (5G) standardization process. Even though the earlier generations are capably of providing coarse location estimates, the achieved accuracy is far from the expected even sub-meter positioning accuracy envisioned in the context of 5G networks. In general, 5G new radio (NR) networks provide a convenient infrastructure for positioning by means of wider bandwidths, larger antenna arrays, and even more densely deployed networks especially at high millimeter wave (mmWave) frequencies. Building on dense 5G NR networks, this thesis focuses on the development of novel network-centric positioning frameworks by exploiting the existing NR reference signals. The contributions in this thesis can be grouped into topics based on the considered frequency ranges and the employed beamforming (BF) schemes therein. First, novel cascaded algorithms for sequential device positioning are proposed assuming 5G NR networks operating at the lower sub-6 GHz frequency range and equipped with digital BF capabilities. In the first stage of the cascaded solution, two sequential estimators are proposed for joint direction of arrival (DoA) and time of arrival (ToA) estimation facilitating the received reference signals. Thereafter, the second-stage sequential estimators employing the obtained DoA and ToA estimates are proposed for joint positioning and network synchronization resulting in not only device location estimates, but also clock parameter estimates that are obtained as a valuable by-product. Such a choice stems from the fact that the ToA estimates are not feasible for positioning as such due to the clock instabilities in low-cost devices and the insufficient level of synchronization in the cellular networks. Second, a similar cascaded algorithm for joint positioning and network synchronization is proposed in the context of dense mmWave 5G networks and fundamentally different analog BFs. In particular, a novel joint DoA and ToA estimator is proposed by fusing information from multiple received beams based on a novel beam-selection method. In addition, the theoretical performance limits are derived and compared to those obtained using the digital BFs. The cascaded framework is completed with the second-stage positioning solution in a similar manner as in the case of digital BFs. The performance of both frameworks is evaluated and analyzed in various scenarios using extensive computer simulations relying on the latest 5G NR numerology and a ray-tracing tool. Overall, this thesis provides valuable insights into practical positioning algorithms and their performance when relying solely on the 5G NR networks and available signalling therein. The obtained results in this thesis indicate that the envisioned sub-meter positioning accuracy is technically feasible using NR-based solutions

Analogic for code estimation and detection

Thesis (S.M.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2005.Includes bibliographical references (p. 125-128).Analogic is a class of analog statistical signal processing circuits that dynamically solve an associated inference problem by locally propagating probabilities in a message-passing algorithm [29] [15]. In this thesis, we study an exemplary embodiment of analogic called Noise-Locked Loop(NLL) which is a pseudo-random code estimation system. The previous work shows NLL can perform direct-sequence spread-spectrum acquisition and tracking functionality and promises orders-of-magnitude win over digital implementations [29]. Most of the research [30] [2] [3] has been focused on the simulation and implementation of probability representation NLL derived from exact form message-passing algorithms. We propose an approximate message-passing algorithm for NLL in log-likelihood ratio(LLR) representation and have constructed its analogic implementation. The new approximate NLL gives shorter acquisition time comparing to the exact form NLL. The approximate message-passing algorithm makes it possible to construct analogic which is almost temperature independent. This is very useful in the design of robust large-scale analogic networks. Generalized belief propagation(GBP) has been proposed to improve the computational accuracy of Belief Propagation [31] [32] [33].(cont.) The application of GBP to NLL promises significantly improvement of the synchronization performance. However, there is no report on circuit implementation. In this thesis, we propose analogic circuits to implement the basic computations in GBP, which can be used to construct general GBP systems. Finally we propose a novel current-mode signal restoration circuit which will be important in scaling analogic to large networks.by Xu Sun.S.M

Investigation of continental drift, phase 1 effort Progress report, 1 Apr. - 30 Sep. 1968

Feasibility of using ultrashort pulse laser ranging and independent clock radio interferometry distance measurement methods to test for existence of continental drif

Clock synchronisation for UWB and DECT communication networks

Synchronisation deals with the distribution of time and/or frequency across a network of nodes dispersed in an area, in order to align their clocks with respect to time and/or frequency. It remains an important requirement in telecommunication networks, especially in Time Division Duplexing (TDD) systems such as Ultra Wideband (UWB) and Digital Enhanced Cordless Telecommunications (DECT) systems. This thesis explores three di erent research areas related to clock synchronisation in communication networks; namely algorithm development and implementation, managing Packet Delay Variation (PDV), and coping with the failure of a master node. The first area proposes a higher-layer synchronisation algorithm in order to meet the specific requirements of a UWB network that is based on the European Computer Manufacturers Association (ECMA) standard. At up to 480 Mbps data rate, UWB is an attractive technology for multimedia streaming. Higher-layer synchronisation is needed in order to facilitate synchronised playback at the receivers and prevent distortion, but no algorithm is de ned in the ECMA-368 standard. In this research area, a higher-layer synchronisation algorithm is developed for an ECMA-368 UWB network. Network simulations and FPGA implementation are used to show that the new algorithm satis es the requirements of the network. The next research area looks at how PDV can be managed when Precision Time Protocol (PTP) is implemented in an existing Ethernet network. Existing literature indicates that the performance of a PDV ltering algorithm usually depends on the delay pro le of the network in which it is applied. In this research area, a new sample-mode PDV filter is proposed which is independent of the shape of the delay profile. Numerical simulations show that the sample-mode filtering algorithm is able to match or out-perform the existing sample minimum, mean, and maximum filters, at differentlevels of network load. Finally, the thesis considers the problem of dealing with master failures in a PTP network for a DECT audio application. It describes the existing master redundancy techniques and shows why they are unsuitable for the specific application. Then a new alternate master cluster technique is proposed along with an alternative BMCA to suit the application under consideration. Network simulations are used to show how this technique leads to a reduction in the total time to recover from a master failure