Modeling a IF double sampling bandpass switched capacitor ΣΔ ADC with a symmetric noise transfer function for WiMAX/WLAN

4G technology aims to revolutionize private and professional communication with its ubiquity and high-speed transmission (averaging 100Mbps). WiMAX and WLAN are two of the high speed access technologies to be used in the 4G mobile communication. Apropos to their high bandwidths, oversampling converters, e.g.ΣΔ ADCs, used for these standards would entail high levels of power consumption. Double sampling technique used in ΣΔ ADCs help in reducing the power consumption, since the actual sampling rate is only half the sampling frequency required to achieve a target resolution. But for conventional modulators, with low pass noise transfer functions (NTF), this benefit is hampered by the introduction of folded noise due to the mismatch of sampling capacitances. This paper presents a novel method of designing IF bandpass switched capacitor (SC)ΣΔ modulators with symmetric NTFs. Such a bandpass NTF is formulated with its center frequency at one-fourth the effective sampling frequency. The symmetricity ensures that the folded noise is `noise-shaped' along with the quantization noise. The idea is verified with a discrete time bandpass ΣΔ modulator modeled using Simulink®, including various nonlinearities, viz. clock jitter, opampnonidealities, and capacitive mismatch effects owing to double sampling and use of a multibitquantizer. Behavioral simulations of the proposed non-ideal model for WiMAX and WLAN, with a bandwith of 10MHz and 11MHz, respectively, achieved a peak resolution greater than 10 bits for each of the standards

Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

An Overview of Cryptography (Updated Version, 3 March 2016)

There are many aspects to security and many applications, ranging from secure commerce and payments to private communications and protecting passwords. One essential aspect for secure communications is that of cryptography...While cryptography is necessary for secure communications, it is not by itself sufficient. This paper describes the first of many steps necessary for better security in any number of situations. A much shorter, edited version of this paper appears in the 1999 edition of Handbook on Local Area Networks published by Auerbach in September 1998

Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology

Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning applications has increased the demand of MEMS-based digital microphones. Mobile devices have several microphones enabling noise canceling, acoustic beamforming and speech recognition. With the development of machine learning applications the interest to integrate sensors with neural networks has increased. This has driven the interest to develop digital microphones in nanometer CMOS nodes where the microphone analog-front end and digital processing, potentially including neural networks, is integrated on the same chip. Traditionally, analog-to-digital converters (ADCs) in digital microphones have been implemented using high order Sigma-Delta modulators. The most common technique to implement these high order Sigma-Selta modulators is switchedcapacitor CMOS circuits. Recently, to reduce power consumption and make them more suitable for tasks that require always-on operation, such as keyword recognition, switched-capacitor circuits have been improved using inverter-based operational amplifier integrators. Alternatively, switched-capacitor based Sigma- Delta modulators have been replaced by continuous time Sigma-Delta converters. Nevertheless, in both implementations the input signal is voltage encoded across the modulator, making the integration in smaller CMOS nodes more challenging due to the reduced voltage supply. An alternative technique consists on encoding the input signal on time (or frequency) instead of voltage. This is what time-encoded converters do. Lately, time-encoding converters have gained popularity as they are more suitable to nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs). VCO-ADCs can be implemented using CMOS inverter based ring oscillators (RO) and digital circuitry. They also show noise-shaping properties. This makes them a very interesting alternative for implementation of ADCs in nanometer CMOS nodes. Nevertheless, two main circuit impairments are present in VCO-ADCs, and both come from the oscillator non-idealities. The first of them is the oscillator phase noise, that reduces the resolution of the ADC. The second is the non-linear tuning curve of the oscillator, that results in harmonic distortion at medium to high input amplitudes. In this thesis we analyze the use of time encoding ADCs for MEMS microphones with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations for the noise transfer function (NTF) of a third order sigma-delta using a second order filter and the NSQ are presented. Secondly, we move our attention to the topic of RO-ADCs. We present a high dynamic range MEMS microphone 130nm CMOS chip based on an open-loop VCO-ADC. This dissertation shows the implementation of the analog front-end that includes the oscillator and the MEMS interface, with a focus on achieving low power consumption with low noise and a high dynamic range. The digital circuitry is left to be explained by the coauthor of the chip in his dissertation. The chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5% at 128 dBSPL with a power consumption of 438μW. After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement an unsampled feedback loop around the oscillator. The objective is to reduce distortion. Additionally phase noise mitigation is achieved. A first topology including an operational amplifier to increase the loop gain is analyzed. The design is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR with an analog power consumption of 600μW. A second topology without the operational amplifier is also analyzed. Two chips are designed with this topology. The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto- digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a power consumption of 482μW. The second chip includes only the oscillator and is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog power consumption is 153μW. To finish this thesis, two circuits that use an FDR with a ring oscillator are presented. The first is a capacity-to-digital converter (CDC). The second is a filter made with an FDR and an oscillator intended for voice activity detection tasks (VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de machine-learning han aumentado la demanda de micrófonos digitales basados en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación de ruido, el beamforming o conformación de haces y el reconocimiento de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde el front-end analógico y el procesamiento digital del micrófono, que puede incluir redes neuronales, está integrado en el mismo chip. Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos digitales han sido implementados utilizando moduladores Sigma-Delta de orden elevado. La técnica más común para implementar estos moduladores Sigma- Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente, para reducir el consumo de potencia y hacerlos más adecuados para las tareas que requieren una operación continua, como el reconocimiento de palabras clave, los convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con el uso de integradores implementados con amplificadores operacionales basados en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas han sido reemplazados por moduladores en tiempo continuo. No obstante, en ambas implementaciones, la señal de entrada es codificada en voltaje durante el proceso de conversión, lo que hace que la integración en nodos CMOS más pequeños sea complicada debido a la menor tensión de alimentación. Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación temporal. Recientemente, los convertidores de codificación temporal han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos que los convertidores Sigma-Delta. Entre los que más interés han despertado encontramos los ADCs basados en osciladores controlados por tensión (VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo (RO) implementados con inversores CMOS y circuitos digitales. Esta familia de convertidores también tiene conformado de ruido. Esto los convierte en una alternativa muy interesante para la implementación de convertidores en nodos CMOS nanométricos. Sin embargo, dos problemas principales están presentes en este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no lineal del oscilador, lo que causa distorsión a amplitudes medias y altas. En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos MEMS, con especial interés en ADCS basados en osciladores de anillo (RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador agrega un orden adicional de conformado de ruido al modulador, mejorando la resolución. En este documento se explica el cuantificador y obtienen las ecuaciones para la función de transferencia de ruido (NTF) de un sigma-delta de tercer orden usando un filtro de segundo orden y el NSQ. En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos el chip de un micrófono MEMS de alto rango dinámico en CMOS de 130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación del front-end analógico que incluye el oscilador y la interfaz con el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La descripción del back-end digital se deja para la tesis del couator del chip. La SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD de 1,5% a 128 dBSPL y un consumo de potencia de 438μW. Finalmente, se analiza el uso de una resistencia dependiente de frecuencia (FDR) para implementar un bucle de realimentación no muestreado alrededor del oscilador. El objetivo es reducir la distorsión. Además, también se logra la mitigación del ruido de fase del oscilador. Se analyza una primera topologia de realimentación incluyendo un amplificador operacional para incrementar la ganancia de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador operacional. Se fabrican y miden dos chips diseñados con esta topologia. El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de 76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el el consumo de potencia analógica es de 153μW. Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador en anillo. El primero es un convertidor de capacidad a digital (CDC). El segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout

Implementing Write Compression in Flash Memory Using Zeckendorf Two-Round Rewriting Codes

Flash memory has become increasingly popular as the underlying storage technology for high-performance nonvolatile storage devices. However, while flash offers several benefits over alternative storage media, a number of limitations still exist within the current technology. One such limitation is that programming (altering a bit from its default value) and erasing (returning a bit to its default value) are asymmetric operations in flash memory devices: a flash memory can be programmed arbitrarily, but can only be erased in relatively large batches of storage bits called blocks, with block sizes ranging from 512K up to several megabytes. This creates a situation where relatively small write operations to the drive can potentially require reading out, erasing, and rewriting many times more data than the initial operation would normally require if that write would result in a bit erase operation. Prior work suggests that the performance impact of these costly block erase cycles can be mitigated by using a rewriting code, increasing the number of writes that can be performed on the same location in memory before an erase operation is required. This paper provides an implementation of this rewriting code, both as a software program written in C and as a SystemVerilog FPGA circuit specification, and discusses many of the additional design considerations that would be necessary to integrate such a rewriting code with current file storage techniques

Development of a street sweeper fleet management system

Street sweeping is a vital public service that not only facilitates traffic flow and improves the appearance of the neighborhoods. It also helps removes debris and dust from the roadways thus enhancing drainage and reducing air pollution. The need for a street sweeper fleet management system is to help improve the efficiency and effectiveness of street sweeping programs. In this research, an application is developed for the management of street sweepers with the aid of a mapping system interface to query and analyze the data collected using Global Positioning System (GPS) devices installed in the sweeper trucks. Based on the functional needs of the system, an architecture is first developed for the system. Then, existing software and hardware components are used as the basis to design the system. Customized interfaces and processes are developed to integrate various system components. The resulting system is expected to provide accurate records of machine activity, improving fleet cost management and vehicle productivity. The system has the capabilities to generate reports and graphical summaries of various aspects of resource allocation and utilization. Examples of such reporting capabilities include records of machine usage and activity including dates, exact times and locations that vehicles start, drive, idle and stop as well as the use of various events such as even when and where the brooms and dust suppression systems were engaged. (Abstract shortened by UMI.)

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

The Treatment of Advanced Persistent Threats on Windows Based Systems

Advanced Persistent Threat (APT) is the name given to individuals or groups who write malicious software (malware) and who have the intent to perform actions detrimental to the victim or the victims' organisation. This thesis investigates ways in which it is possible to treat APTs before, during and after the malware has been laid down on the victim's computer. The scope of the thesis is restricted to desktop and laptop computers with hard disk drives. APTs have different motivations for their work and this thesis is agnostic towards their origin and intent. Anti-malware companies freely present the work of APTs in many ways but summarise mainly in the form of white papers. Individually, pieces of these works give an incomplete picture of an APT but in aggregate it is possible to construct a view of APT families and pan-APT commonalities by comparing and contrasting the work of many anti-malware companies; it as if there are alot of the pieces of a jigsaw puzzle but there is no box lid available with the complete picture. In addition, academic papers provide proof of concept attacks and observations, some of which may become used by malware writers. Gaps in, and extensions to, the public knowledge may be filled through inference, implication, interpolation and extrapolation and form the basis for this thesis. The thesis presents a view of where APTs lie on windows-based systems. It uses this view to create and build generic views of where APTs lie on Hard Disc Drives on Windows based systems using the Lockheed Martin Cyber Kill Chain. This is then used to treat APTs on Windows based IT systems using purpose-built software in such a way that the malware is negated by. The thesis does not claim to find all malware on but it demonstrates how to increase the cost of doing business for APTs, for example by overwriting unused disc space so APTs cannot place malware there. The software developed was able to find Indicators of Compromise on all eight Hard Disc Drives provided for analysis. Separately, from a corpus of 228 files known to be associated with malware it identified approximately two thirds as Indicators of Compromise

Innovative Techniques for Testing and Diagnosing SoCs

We rely upon the continued functioning of many electronic devices for our everyday welfare, usually embedding integrated circuits that are becoming even cheaper and smaller with improved features. Nowadays, microelectronics can integrate a working computer with CPU, memories, and even GPUs on a single die, namely System-On-Chip (SoC). SoCs are also employed on automotive safety-critical applications, but need to be tested thoroughly to comply with reliability standards, in particular the ISO26262 functional safety for road vehicles. The goal of this PhD. thesis is to improve SoC reliability by proposing innovative techniques for testing and diagnosing its internal modules: CPUs, memories, peripherals, and GPUs. The proposed approaches in the sequence appearing in this thesis are described as follows: 1. Embedded Memory Diagnosis: Memories are dense and complex circuits which are susceptible to design and manufacturing errors. Hence, it is important to understand the fault occurrence in the memory array. In practice, the logical and physical array representation differs due to an optimized design which adds enhancements to the device, namely scrambling. This part proposes an accurate memory diagnosis by showing the efforts of a software tool able to analyze test results, unscramble the memory array, map failing syndromes to cell locations, elaborate cumulative analysis, and elaborate a final fault model hypothesis. Several SRAM memory failing syndromes were analyzed as case studies gathered on an industrial automotive 32-bit SoC developed by STMicroelectronics. The tool displayed defects virtually, and results were confirmed by real photos taken from a microscope. 2. Functional Test Pattern Generation: The key for a successful test is the pattern applied to the device. They can be structural or functional; the former usually benefits from embedded test modules targeting manufacturing errors and is only effective before shipping the component to the client. The latter, on the other hand, can be applied during mission minimally impacting on performance but is penalized due to high generation time. However, functional test patterns may benefit for having different goals in functional mission mode. Part III of this PhD thesis proposes three different functional test pattern generation methods for CPU cores embedded in SoCs, targeting different test purposes, described as follows: a. Functional Stress Patterns: Are suitable for optimizing functional stress during I Operational-life Tests and Burn-in Screening for an optimal device reliability characterization b. Functional Power Hungry Patterns: Are suitable for determining functional peak power for strictly limiting the power of structural patterns during manufacturing tests, thus reducing premature device over-kill while delivering high test coverage c. Software-Based Self-Test Patterns: Combines the potentiality of structural patterns with functional ones, allowing its execution periodically during mission. In addition, an external hardware communicating with a devised SBST was proposed. It helps increasing in 3% the fault coverage by testing critical Hardly Functionally Testable Faults not covered by conventional SBST patterns. An automatic functional test pattern generation exploiting an evolutionary algorithm maximizing metrics related to stress, power, and fault coverage was employed in the above-mentioned approaches to quickly generate the desired patterns. The approaches were evaluated on two industrial cases developed by STMicroelectronics; 8051-based and a 32-bit Power Architecture SoCs. Results show that generation time was reduced upto 75% in comparison to older methodologies while increasing significantly the desired metrics. 3. Fault Injection in GPGPU: Fault injection mechanisms in semiconductor devices are suitable for generating structural patterns, testing and activating mitigation techniques, and validating robust hardware and software applications. GPGPUs are known for fast parallel computation used in high performance computing and advanced driver assistance where reliability is the key point. Moreover, GPGPU manufacturers do not provide design description code due to content secrecy. Therefore, commercial fault injectors using the GPGPU model is unfeasible, making radiation tests the only resource available, but are costly. In the last part of this thesis, we propose a software implemented fault injector able to inject bit-flip in memory elements of a real GPGPU. It exploits a software debugger tool and combines the C-CUDA grammar to wisely determine fault spots and apply bit-flip operations in program variables. The goal is to validate robust parallel algorithms by studying fault propagation or activating redundancy mechanisms they possibly embed. The effectiveness of the tool was evaluated on two robust applications: redundant parallel matrix multiplication and floating point Fast Fourier Transform

Quadrature sigma-delta modulators for reconfigurable A/D interface and dynamic spectrum access: analysis, design principles and digital post-processing

In the course of development of wireless communications and its modern applications, such as cloud technologies and increased consumption and sharing of multimedia, the radio spectrum has become increasingly congested. However, temporarily and spatially underused spectrum exists at the same time. For increasing the efficiency of spectrum usage, the concept of dynamic spectrum access (DSA) has been proposed. Ultimately, the DSA principle should be exploited also in cognitive radio (CR) receivers. Herein, this paradigm is approached from the receiver architecture point-of-view, considering software-defined radio (SDR) as a platform for the future DSA and CR devices. Particularly, an analog-to-digital converter (ADC) architecture exploiting quadrature ΣΔ modulator (QΣΔM) is studied in detail and proposed as a solution for the A/D interface, being identified as a performance bottleneck in SDRs. By exploiting a complex valued noise transfer function (NTF) enabled by the QΣΔM, the quantization precision of the ADC can be efficiently and flexibly focused on the frequency channels and the signals to be received and detected. At the same time, with a traditional non-noise-shaping ADC, the precision is distributed equally for the whole digitized frequency band containing also noninteresting signals. With a single QΣΔM, it is also possible to design a multiband NTF, allowing reception of multiple noncontiguous frequency channels without parallel receiver chains. Furthermore, with the help of digital control, the QΣΔM response can be reconfigured during operation. These capabilities fit in especially well with the above mentioned DSA and CR schemes, where the temporarily and spatially available channels might be scattered in frequency. From the implementation point-of-view, the effects of inherent implementation inaccuracies in the QΣΔM design need to be thoroughly understood. In this thesis, novel closed-form matrix-algebraic expressions are presented for analyzing the transfer functions of a general multistage QΣΔM with arbitrary number of arbitrary-order stages. Altogether, the signal response of an I/Q mismatched QΣΔM has four components. These are the NTF, an image noise transfer function, a signal transfer function (STF) and an image signal transfer function. The image transfer functions are provoked by the I/Q mismatches and define the frequency profile of the generated mirror-frequency interference (MFI), potentially deteriorating the quality of the received signal. This contribution of the thesis increases the understanding of different QΣΔM structures and allows the designers to study the effects of the implementation inaccuracies in closed form. In order to mitigate the MFI and improve the signal reception, a mirror-frequency rejecting STF design is proposed herein. This design is found to be effective against I/Q mismatches taking place in the feedback branches of the QΣΔM. This is shown with help of the closed-form analysis and confirmed with computer simulations on realistic reception scenarios. When a mismatch location independent MFI suppression is the desired option, it is a logical choice to do this processing in a digital domain, after the whole analog receiver front-end. However, this sets demands for the information to be digitized, i.e., the source of the MFI should be available also in the digital domain. For this purpose, a novel multiband transfer function design is proposed herein. In addition, a QΣΔM specific digital MFI compensation algorithm is developed. The compensation performance is illustrated in practical single- and multiband reception scenarios, considering desired signal bandwidths up to 20 MHz. In the multiband scenario, allowing reception and detection of noncontiguous frequency channels with a single receiver chain, the digital compensation processing is done sub-bandwise, securing reliable functionality also under strongly frequency-selective interference. In the applied single- and multistage QΣΔM architectures, the I/Q mismatches are considered in all the QΣΔM branches as well as in the preceding receiver front-end, modeling the challenging and realistic scenario where the whole receiver chain includes cascaded in-phase/quadrature (I/Q) mismatch sources. As a whole, developing digital MFI compensation is a significant step towards practical receiver implementations with QΣΔM ADCs. In consequence, this allows the exploitation of the multiband and reconfigurability properties. The proposed design can be implemented without additional analog components and is straightforwardly reconfigurable in dynamic signal conditions typical for DSA and CR systems, e.g., in case of frequency hand-off because of a primary user appearance. In addition, the digital post-compensation of the MFI eases the strict demands for the matching of the analog circuits in SDRs