A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing

High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don\u27t-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.2007 IEEE International Test Conference, 21-26 October 2007, Santa Clara, CA, US

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.2009 Asian Test Symposium, 23-26 November 2009, Taichung, Taiwa

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC\u2799 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.2011 Asian Test Symposium, 20-23 November 2011, New Delhi, Indi

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.2008 17th Asian Test Symposium (ATS 2008), 24-27 November 2008, Sapporo, Japa

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

ITC : 2012 IEEE International Test Conference , 5-8 Nov. 2012 , Anaheim, CA, USAIn return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency

Double resonant absorption measurement of acetylene symmetric vibrational states probed with cavity ring down spectroscopy

A novel mid-infrared/near-infrared double resonant absorption setup for studying infrared-inactive vibrational states is presented. A strong vibrational transition in the mid-infrared region is excited using an idler beam from a singly resonant continuous-wave optical parametric oscillator, to populate an intermediate vibrational state. High output power of the optical parametric oscillator and the strength of the mid-infrared transition result in efficient population transfer to the intermediate state, which allows measuring secondary transitions from this state with a high signal-to-noise ratio. A secondary, near-infrared transition from the intermediate state is probed using cavity ring down spectroscopy, which provides high sensitivity in this wavelength region. Due to the narrow linewidths of the excitation sources, the rovibrational lines of the secondary transition are measured with sub-Doppler resolution. The setup is used to access a previously unreported symmetric vibrational state of acetylene, $\nu_1+\nu_2+\nu_3+\nu_4^1+\nu_5^{-1}$ in the normal mode notation. Single-photon transitions to this state from the vibrational ground state are forbidden. Ten lines of the newly measured state are observed and fitted with the linear least-squares method to extract the band parameters. The vibrational term value was measured to be at 9775.0018(45) $\text{cm}^{-1}$, the rotational parameter $B$ was 1.162222 $\text{cm}^{-1}$, and the quartic centrifugal distortion parameter $D$ was 3.998(62)$\times 10^{-6} \text{cm}^{-1}$, where the numbers in the parenthesis are one-standard errors in the least significant digits

A novel scan segmentation design method for avoiding shift timing failure in scan testing

ITC : 2011 IEEE International Test Conference , 20-22 Sep. 2011 , Anaheim, CA, USAHigh power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC