A simple bandgap reference based on VGO extraction with single-temperature trimming

Bandgap references are widely used in analog and mixed-signal systems to provide temperature-independent voltage or current reference. In traditional bandgap structure, the base-emitter voltage VBE of a diode is used to generate a complementary to absolute temperature (CTAT) voltage, which reduces as temperature increases. The base-emitter voltage difference ∆VBE between two diodes with the same current but different emitter areas supplies a proportional to absolute temperature (PTAT) voltage. With the proper adjustment of the coefficients of VBE and ∆VBE in a voltage summer, the temperature dependency of the summed voltage can be mostly canceled out and the output voltage can achieve a relative temperature-constant property. However, even though the linear terms of temperature-dependent components in PTAT and CTAT expressions can be canceled out, there are still some high order terms left, which still affect temperature dependency. For this reason, a first-order bandgap reference with only PTAT and CTAT linear term compensation cannot achieve a sufficiently low temperature coefficient (TC), normally ranging from 10ppm/°C to over 100ppm/°C. To achieve higher precision and lower TC, the high order terms also need to be considered and compensated by some techniques. This thesis study describes the development of a high order bandgap structure, including the initial thinking, design flow, equation derivation, circuit implementation, and simulation result

Low temperature coefficient bandgap voltage reference generator

The maximum achievable performance of almost all mixed-signal and radio frequency systems is dependent on the accuracy of voltage references. The bandgap voltage of silicon at zero Kelvin, VGO is a physical constant with unit Volts. It is independent of process, supply voltage and temperature variations. This work proposes a strategy for extracting VGO and expressing it at the output of a voltage reference circuit. The concept is implemented in UMC 65nm process and the simulation results indicate that the circuit design can achieve very low temperature coefficients (\u3c1ppm/°C). The proposed concept is validated using measurements and the associated constraints are carefully investigated. The measured output voltage reference of the two tested units record a temperature coefficient of 3.4ppm/°C and 4.57ppm/°C across the industrial temperature range (-40°C to 85°C)

CMOS analog-digital circuit components for low power applications

Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction circuits for energy harvester. The main contribution of this work is the realization of low power consumption and high efficient circuit components employable in a management circuit for piezoelectricbased energy harvester. This thesis focuses on the development of current references and operational amplifiers addressing low power demands. A brief literature review is conducted on the components necessary for the power extraction circuit, including introduction to CMOS technology design and research of known low power circuits. It is presented with multiple implementations for voltage and current references, as well for operational amplifier designs. A self-biased current reference, capable of driving the remaining harvesting circuit, is designed and verified. A novel operational amplifier is proposed by the use of a minimum current selector circuit topology. It is a three-stage amplifier with an AB class output stage, comprised by a translinear circuit. The circuit is designed, taking into consideration noise reduction. The circuit components are designed based on the 0.35mm CMOS technology. A physical layout is developed for fabrication purposes. This technology was chosen with consideration of robustness, costliness and performance. The current reference is capable of outputting a stable 12nA current, which may remain stable in a broad range of power supply voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW, with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração de energia com base num elemento piezoelétrico. Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um amplificador operacional com baixa exigência de consumo. Uma revisão da literatura é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações de referência de tensão e corrente são consideradas, e amplificadores operacionais também. Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e verificada. Um amplificador operacional original é proposto com uma topologia de seleção de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na sua implementação. Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em conta o seu custo versus desempenho. A referência de corrente produz uma corrente de 12nA, permanecendo estável para tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima mantida no estágio de saída

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

Design of a silicon ASIC chip for crystal oscillator oven circuitry

Stability of electronic circuits with temperature variations is very critical. Crystal oscillator circuits are one such application which demand high frequency stability with variation in temperature. There are several existing methods to control these variations. Ovenized crystal oscillators is one such method in which the crystal oscillator circuit is heated to a predetermined temperature with the help of a surrounding oven and maintained at that temperature with the help of a feedback mechanism. However, having the heating mechanism on the silicon substrate itself has several advantages over conventional oven technique. In this thesis, an integrated circuit used for controlling the temperature of the substrate is designed. A prototype system is developed and fabricated in MOSIS 1.2[Mu] BiCMOS, N-well process. The ASIC circuit is then tested and its performance is compared to the simulation results

Fully Integrated Voltage Reference Circuits

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2014(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2014Gerilim referans devreleri, elektriksel sistemlerde diğer alt blokların çalışmaları için kararlı bir çalışma noktası üretmeleri sebebiyle veri dönüştürücüler (ADC - DAC), frekans sentezleyiciler, DC-DC ve AC-DC dönüştürücüler ve lineer regülatörler gibi pek çok elektriksel sistemin en temel yapı bloklarındandır. İdeal olarak, üretilen bu referans noktası, sıcaklık, üretim süreçleri, besleme gerilim degişimleri ve yükleme etkileri gibi çalışma koşullarından etkilenmemelidir. Bir referans devresinin doğruluğu bahsedilen çalışma koşullarının etkisiyle mutlak değerinden ne kadar saptığı olarak tanımlanır. Modern haberleşme sistemleri ve tüketici ürünlerindeki gelişmeler ile birlikte yüksek entegrasyon ve doğruluklu sistemlere olan talep artmıştır. Tümdevre sistemlerinde, alt blokların çalışma noktalarını belirlemesi nedeniyle özellikle referans devrelerinin performansları bütün sistemin performansının belirlenmesinde önemli rol oynamaktadır. Dolayısıyla yüksek performanslı sistemlere olan talep, bu performansların elde edilmesi için kullanılan düşük geometrili üretim teknolojilerine uygun, yani giderek azalan besleme gerilimleri ile çalışabilecek yüksek doğruluklu referans devrelerine olan talebi de arttırmıştır. Bu nedenle bu çalışmada gerilim referans devre topolojilerine odaklanılmıştır. Bu doğrultuda, öncelikle yüksek doğruluklu, düşük gürültülü gerilim refereans devre topolojileri üzerinde çalışılarak 0.35 um CMOS teknoljisinde farklı tasarımlar yapılmıştır. Bu aşamada temel hedef, yüksek dogrulukluk olarak belirenmiş ve yapılan tasarımlarda, üretim sonrası ayarlamalardan sonra sıcaklık katsayısı 3 ppm/C olabilecek devreler tasarlanmıştır. Ancak, 0.35 um CMOS üretim teknolojisi kullanılması ve kullanılan topolojiler dolayısıyla, devrelerin çalışabileceği minimum besleme gerilim seviyesi 1.8 V ile sınırlı kalmıştır. Devrelerin çektikleri akımlar ise 20-30 uA seviyesindedir. Bu tasarımlar sırasında (triple-well üretim teknlojileri için), önerilen blok gövde izolasyon stratejisi, tasarımı yapılan devrenin gövdesinin tümdevrenin geri kalan kısmından ters kutuplanmış bir jonksiyon diyodu sayesinde izole edilmesine dayanmaktadır ve devrenin gövde gürültüsünden etkilenmesini önemli ölçüde azaltmaktadır. Son olarak, çoğunlukla osilatör devrelerinde uygulanan anahtarlamalı kutuplama tekniği uygulanarak devrelerin düşük frekans gürültü performansının iyileştirilmesi amaçlanmıştır. Çalışmanın geri kalan kısmında, düşük besleme gerilimleriyle çalışabilecek mikron-altı üretim teknolojilerine uygun gerilim referans devre topolojileri üzerine odaklanılmıştır. Bu doğrultuda, iki yeni düşük besleme gerilimli ve düşük güç tüketimli gerilim referans devre topolojisi önerilmiştir. Önerilen topolojiler, 0.18 um CMOS üretim teknolojisinde gerçeklenmiştir. Ölçüm sonuçları, tasarlanan gerilim refarans devrelerinin 0.65 V besleme gerilimi ile çalışabildiğini göstermiştir. Önerilen devre topolojileri ile 0-120 C sıcaklık aralığında, sıcaklık katsayısı 50 ppm/C olan 193 mV seviyesinde referans gerilimleri elde edilmiştir. Devrelerin güç tüketimleri sırasıyla 0.3 uW ve 0.4 uW iken kapladıkları alan 0.2 mm^2 ve 0.08 mm^2 dir. Sonuç olarak, önerilen devre topolojileri ile literatürde yer alan diğer 1V-altı referans devreleri ile karşılatrılabilir seviyede sıcaklık katsayısı olan referans gerilimleri çok daha düşük güç harcamasıyla elde edilmiştir.Voltage references are one of the basic building blocks of many SoCs and mixed-signal ICs such as data converters, voltage regulators and operational amplifiers as they constitute a stable reference voltage for other sub-circuits to generate predictable and repeatable results. Ideally, this reference point should not change with external influences or operating conditions such as temperature, fabrication process variations, power supply variations and transient loading effects. Along with the rapid development of modern communication systems and consumer products, which constitutes the main market for semiconductor industry, the market demand for these System on Chip (SoC) or Mixed Signal ICs to have lower power consumption, higher accuracy and lower cost, and thus, higher integration. Since the performance of the whole system depends strongly to the performance of the reference circuit, this work is focused on fully integrated voltage reference architectures. With this motivation, firstly, different kinds of high precision low noise voltage reference circuits are designed in standard 0.35 um CMOS technology that we have more experience and knowledge of. The essential goal of these studies was high precision and temperature coefficient of the designed voltage reference circuits are on the order of 3 ppm/C with trimming after production. However, since 0.35 um CMOS technology is used in these designs and also due to the chosen topologies their minimum supply voltage can be down to 1.8 V and while current consumption is on the order of 20-30 uA. In the design of the this voltage reference block bulk isolation technique is proposed (for triple-well CMOS processes), in which system blocks are bulk isolated by a reverse biased junction diode from the rest of the die to drastically reduce substrate noise coupling. This is especially important if a very low power voltage reference is designed in a very noisy SoC. Moreover, the switched biasing technique, which is mostly applied to the oscillators, is also implemented to the designed BGR in order to improve the low noise performance of the circuit. The rest of the thesis is focused on new voltage reference topologies that are appropriate for sub-micron technologies operating with low supply voltages. With this motivation two new low voltage and low power voltage reference topologies are proposed. The proposed voltage reference topologies are implemented and fabricated in 0.18 um CMOS technology. Measurement results show that the proposed voltage reference circuits are working properly down to 0.65 V and achieve an output voltage of 193 mV with a temperature coefficient on the order of 50 ppm/C in the temperature range of 0-120C. The total power consumption of the two designed voltage references are 0.3 uW and 0.4 uW at 27 C, while occupying the area of 0.2 mm^2 and 0.08 mm^2, respectively. As a result, the proposed voltage reference topologies generate a reference voltage with comparable level of temperature coefficient and quite low power consumption with respect to the other sub-1V voltage reference circuits reported in the literature.DoktoraPh

Semitransparent perovskite solar cells for perovskite-based tandem photovoltaics

Erneuerbare Energietechnologien auf der Grundlage der Photovoltaik werden in Zukunft eine bedeutende Rolle bei der Deckung des weltweiten Energiebedarfs spielen. Dazu muss der Wirkungsgrad der etablierten und marktbeherrschenden Photovoltaik-Technologie - kristallinem Silizium (c-Si) - erhöht werden. Der Wirkungsgrad von c-Si-Solarzellen ist jedoch bereits nahe an seiner fundamentalen Grenze von ≈29%, und daher stellen weitere Verbesserungen aus wissenschaftlicher Sicht eine Herausforderung dar. Eine Strategie zur weiteren Verbesserung des Wirkungsgrades ist die Kombination eines Halbleiters mit hoher Bandlücke (≈1.7 eV) mit einer c-Si-Einfachsolarzelle (1.1 eV) in einer Tandemkonfiguration mit vier Anschlüssen (4T). Vielversprechende Kandidaten sind Organometall-Halogenid-Perowskit-Materialien, die in letzter Zeit aufgrund ihrer potenziell niedrigen Herstellungskosten und hervorragenden optoelektronischen Eigenschaften große Aufmerksamkeit hervorgerufen haben. Perowskit/c-Si-Tandemsolarzellen haben bereits fast die fundamentale Wirkungsgrad-Grenze von c-Si-Single-Junction-Solarzellen überschritten, wobei weitere Verbesserungen absehbar sind. Um den Wirkungsgrad von Perowskit/c-Si-Tandemsolarzellen weiter zu verbessern, müssen einige zentrale Herausforderungen bewältigt werden. Diese Herausforderungen können in optische und elektrische Verluste kategorisiert werden. Zu den optischen Verlusten gehören parasitäre Absorptions- (vorwiegend durch die Elektroden aus transparentem leitfähigem Oxid (TCO)) und Reflexionsverluste innerhalb des Schichtstapels sowie die Verwendung einer nicht idealen Bandlücke des Perowskit-Absorbers. Elektrische Verluste entstehen durch nichtstrahlende Rekombinationsprozesse innerhalb des Bulk-Materials oder an den Grenzflächen innerhalb des Perowskit-Schichtstapels sowie durch nicht optimale Extraktion der erzeugten Ladungsträger. Der Schwerpunkt dieser Arbeit liegt auf der Minimierung der optischen Verluste, indem ihr Ursprung untersucht und neue Strategien zu ihrer Überwindung entwickelt werden. Als Ausgangspunkt wird eine neuartige hauseigene und vielseitige, bei niedrigen Temperaturen prozessierbare, auf Nanopartikeln basierende Elektronentransportschicht entwickelt, um Perowskit-Einfachsolarzellen auf TCOs mit geringer parasitärer Absorption herzustellen. Perowskit-Solarzellen mit dieser Elektronentransportschicht weisen Wirkungsgrade von über 18% auf. Weiterhin werden in dieser Arbeit zur weiteren Verbesserung des Lichteinfangs in Tandem-Solarzellen neuartige nanophotonische Frontelektroden und alternative TCOs entwickelt. Zunächst wird gezeigt, dass die nanophotonischen Frontelektroden nicht nur die Kurzschlussstromdichte in der Perowskit-Top-Solarzelle verbessern, sondern auch die Transmission im nahen Infrarot-Bereich erhöhen und damit den Wirkungsgrad der c-Si-Bottom-Solarzelle stark verbessern. Zweitens werden qualitativ hochwertige alternative TCOs mit einer hauseigenen Sputter-Technik erforscht, die in Bezug auf Reflexions- und parasitäre Absorptionsverluste kommerziell erhältliche TCOs übertreffen. Diese Konzepte werden angewendet um hocheffiziente 4T-Perowskit/c-Si-Tandemsolarzellen mit Wirkungsgraden von bis zu 27.3% herzustellen, was nicht nur den derzeitigen Rekord-Wirkungsgrad von c-Si-Einfachsolarzellen übertrifft, sondern auch einer der bisher höchsten Werte für 4T-Perowskit/c-Si-Tandemarchitekturen ist. Darüber hinaus wird zum ersten Mal eine detaillierte experimentelle Untersuchung der optimalen Bandlücke des Perowskit-Absorbers in realistischen \u27state-of-the-art‘ 4T-Perowskit/c-Si und Perowskit/CIGS-Tandemsolarzellen durchgeführt. Es wird gezeigt, dass ein breiter Bereich von Bandlücken zwischen 1.65-1.74 eV zu ähnlichen Wirkungsgraden führt, was die Anforderungen an die exakte Bandlücke des Perowskit-Absorbers in hocheffizienten Tandemsolarzellen lockert

Novel sources of near- and mid-infrared femtosecond pulses for applications in gas sensing, pulse shaping and material processing

In this thesis the design, construction process and the performance of two femtosecond optical parametric oscillators and one second–harmonic generation femtosecond pulse shaper is described. One oscillator was applied to gas sensing while potential applications of other devices are outlined. ATi:sapphire oscillator was used to pump a periodically–poled lithium niobate– based optical parametric oscillator. This signal–resonant device was configured to produce broadband idler pulses tunable in the range of 2.7–3.4 μm. This wavelength coverage was matched to the ν3 optical absorption band of methane, and Fourier–transform spectroscopy of a CH4:N2 mixture was implemented by employing a mid–IR silica photonic bandgap fibre simultaneously as a gas cell and an optical waveguide. Methane sensing below a 1% concentration was demonstrated and the main limiting factors were identified and improvements suggested. Another optical parametric oscillator was demonstrated which was pumped by a commercial Yb:fibre master oscillator/power amplifier system and was based on a periodically–poled lithium niobate crystal. The signal was tunable between 1.42–1.57 μm and was intended as a source for a subsequent project for waveguide writing in silicon. The oscillator was a novel long–cavity device operating at 15 MHz. The 130 nJ pump pulse energies allowed for 21 nJ signal pulses at a pump power of 2 W. The performance of the oscillator was characterised via temporal and spectral measurements and the next steps of its development are outlined. Finally a pulse shaper based on second harmonic generation in a grating– engineered periodically–poled lithium niobate crystal was demonstrated. Pulses from a 1.53 μm femtosecond Er:fibre laser were compressed and then used as the input to the shaper. The performance of the shaper was tested by performing cross–correlation frequency–resolved optical gating measurements on the output second harmonic pulses and this confirmed the successful creation of multiple pulses and other tailored shapes including square and chirped pulses, agreeing well with theoretical calculations