2,055 research outputs found
Exact parallel plurality voting algorithm for totally ordered object space fault-tolerant systems
Plurality voter is one of the commonest voting methods for decision making in highly-reliable applications in which the reliability and safety of the system is critical. To resolve the problem associated with sequential plurality voter in dealing with large number of inputs, this paper introduces a new generation of plurality voter based on parallel algorithms. Since parallel algorithms normally have high processing speed and are especially appropriate for large scale systems, they are therefore used to achieve a new parallel plurality voting algorithm by using (n/log n) processors on EREW shared-memory PRAM. The asymptotic analysis of the new proposed algorithm has demonstrated that it has a time complexity of O (log n) which is less than time complexity of sequential plurality algorithm, i.e. Ω (n log n)
A Reliable and Cost-Efficient Auto-Scaling System for Web Applications Using Heterogeneous Spot Instances
Cloud providers sell their idle capacity on markets through an auction-like
mechanism to increase their return on investment. The instances sold in this
way are called spot instances. In spite that spot instances are usually 90%
cheaper than on-demand instances, they can be terminated by provider when their
bidding prices are lower than market prices. Thus, they are largely used to
provision fault-tolerant applications only. In this paper, we explore how to
utilize spot instances to provision web applications, which are usually
considered availability-critical. The idea is to take advantage of differences
in price among various types of spot instances to reach both high availability
and significant cost saving. We first propose a fault-tolerant model for web
applications provisioned by spot instances. Based on that, we devise novel
auto-scaling polices for hourly billed cloud markets. We implemented the
proposed model and policies both on a simulation testbed for repeatable
validation and Amazon EC2. The experiments on the simulation testbed and the
real platform against the benchmarks show that the proposed approach can
greatly reduce resource cost and still achieve satisfactory Quality of Service
(QoS) in terms of response time and availability
Survivable algorithms and redundancy management in NASA's distributed computing systems
The design of survivable algorithms requires a solid foundation for executing them. While hardware techniques for fault-tolerant computing are relatively well understood, fault-tolerant operating systems, as well as fault-tolerant applications (survivable algorithms), are, by contrast, little understood, and much more work in this field is required. We outline some of our work that contributes to the foundation of ultrareliable operating systems and fault-tolerant algorithm design. We introduce our consensus-based framework for fault-tolerant system design. This is followed by a description of a hierarchical partitioning method for efficient consensus. A scheduler for redundancy management is introduced, and application-specific fault tolerance is described. We give an overview of our hybrid algorithm technique, which is an alternative to the formal approach given
Novel fault tolerant Multi-Bit Upset (MBU) Error-Detection and Correction (EDAC) architecture
Desde el punto de vista de seguridad, la certificación aeronáutica de
aplicaciones críticas de vuelo requiere diferentes técnicas que son usadas
para prevenir fallos en los equipos electrónicos. Los fallos de tipo hardware
debido a la radiación solar que existe a las alturas standard de vuelo, como
SEU (Single Event Upset) y MCU (Multiple Bit Upset), provocan un cambio
de estado de los bits que soportan la información almacenada en memoria.
Estos fallos se producen, por ejemplo, en la memoria de configuración de
una FPGA, que es donde se definen todas las funcionalidades. Las técnicas
de protección requieren normalmente de redundancias que incrementan el
coste, número de componentes, tamaño de la memoria y peso.
En la fase de desarrollo de aplicaciones críticas de vuelo, generalmente
se utilizan una serie de estándares o recomendaciones de diseño como
ABD100, RTCA DO-160, IEC62395, etc, y diferentes técnicas de protección
para evitar fallos del tipo SEU o MCU. Estas técnicas están basadas en
procesos tecnológicos específicos como memorias robustas, codificaciones
para detección y corrección de errores (EDAC), redundancias software,
redundancia modular triple (TMR) o soluciones a nivel sistema.
Esta tesis está enfocada a minimizar e incluso suprimir los efectos de los
SEUs y MCUs que particularmente ocurren en la electrónica de avión como
consecuencia de la exposición a radiación de partículas no cargadas (como
son los neutrones) que se encuentra potenciada a las típicas alturas de
vuelo. La criticidad en vuelo que tienen determinados sistemas obligan a que
dichos sistemas sean tolerantes a fallos, es decir, que garanticen un
correcto funcionamiento aún cuando se produzca un fallo en ellos. Es por
ello que soluciones como las presentadas en esta tesis tienen interés en el
sector industrial.
La Tesis incluye una descripción inicial de la física de la radiación
incidente sobre aeronaves, y el análisis de sus efectos en los componentes
electrónicos aeronaúticos basados en semiconductor, que desembocan en
la generación de SEUs y MCUs. Este análisis permite dimensionar
adecuadamente y optimizar los procedimientos de corrección que se
propongan posteriormente.
La Tesis propone un sistema de corrección de fallos SEUs y MCUs que
permita cumplir la condición de Sistema Tolerante a Fallos, a la vez que
minimiza los niveles de redundancia y de complejidad de los códigos de
corrección. El nivel de redundancia es minimizado con la introducción del
concepto propuesto HSB (Hardwired Seed Bits), en la que se reduce la
información esencial a unos pocos bits semilla, neutros frente a radiación.
Los códigos de corrección requeridos se reducen a la corrección de un único
error, gracias al uso del concepto de Distancia Virtual entre Bits, a partir del
cual será posible corregir múltiples errores simultáneos (MCUs) a partir de
códigos simples de corrección.
Un ejemplo de aplicación de la Tesis es la implementación de una
Protección Tolerante a Fallos sobre la memoria SRAM de una FPGA. Esto
significa que queda protegida no sólo la información contenida en la
memoria sino que también queda auto-protegida la función de protección
misma almacenada en la propia SRAM. De esta forma, el sistema es capaz
de auto-regenerarse ante un SEU o incluso un MCU, independientemente
de la zona de la SRAM sobre la que impacte la radiación. Adicionalmente,
esto se consigue con códigos simples tales como corrección por bit de
paridad y Hamming, minimizando la dedicación de recursos de computación
hacia tareas de supervisión del sistema.For airborne safety critical applications certification, different techniques
are implemented to prevent failures in electronic equipments. The HW
failures at flying heights of aircrafts related to solar radiation such as SEU
(Single-Event-Upset) and MCU (Multiple Bit Upset), causes bits alterations
that corrupt the information at memories. These HW failures cause errors, for
example, in the Configuration-Code of an FPGA that defines the
functionalities. The protection techniques require classically redundant
functionalities that increases the cost, components, memory space and
weight.
During the development phase for airborne safety critical applications,
different aerospace standards are generally recommended as ABD100,
RTCA-DO160, IEC62395, etc, and different techniques are classically used
to avoid failures such as SEU or MCU. These techniques are based on
specific technology processes, Hardened memories, error detection and
correction codes (EDAC), SW redundancy, Triple Modular Redundancy
(TMR) or System level solutions.
This Thesis is focussed to minimize, and even to remove, the effects of
SEUs and MCUs, that particularly occurs in the airborne electronics as a
consequence of its exposition to solar radiation of non-charged particles (for
example the neutrons). These non-charged particles are even powered at
flying altitudes due to aircraft volume. The safety categorization of different
equipments/functionalities requires a design based on fault-tolerant approach
that means, the system will continue its normal operation even if a failure
occurs. The solution proposed in this Thesis is relevant for the industrial
sector because of its Fault-tolerant capability.
Thesis includes an initial description for the physics of the solar radiation
that affects into aircrafts, and also the analyses of their effects into the
airborne electronics based on semiconductor components that create the
SEUs and MCUs. This detailed analysis allows the correct sizing and also
the optimization of the procedures used to correct the errors.
This Thesis proposes a system that corrects the SEUs and MCUs
allowing the fulfilment of the Fault-Tolerant requirement, reducing the
redundancy resources and also the complexity of the correction codes. The
redundancy resources are minimized thanks to the introduction of the
concept of HSB (Hardwired Seed Bits), in which the essential information is
reduced to a few seed bits, neutral to radiation. The correction codes
required are reduced to the correction of one error thanks to the use of the
concept of interleaving distance between adjacent bits, this allows the
simultaneous multiple error correction with simple single error correcting
codes.
An example of the application of this Thesis is the implementation of the
Fault-tolerant architecture of an SRAM-based FPGA. That means that the
information saved in the memory is protected but also the correction
functionality is auto protected as well, also saved into SRAM memory. In this
way, the system is able to self-regenerate the information lost in case of
SEUs or MCUs. This is independent of the SRAM area affected by the
radiation. Furthermore, this performance is achieved by means simple error
correcting codes, as parity bits or Hamming, that minimize the use of
computational resources to this supervision tasks for system.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Luis Alfonso Entrena Arrontes.- Secretario: Pedro Reviriego Vasallo.- Vocal: Mª Luisa López Vallej
Towards Human Society-inspired Decentralized DNN Inference
In human societies, individuals make their own decisions and they may select if and who may influence it, by e.g., consulting with people of their acquaintance or experts of a field. At a societal level, the overall knowledge is preserved and enhanced by individual person empowerment, where complicated consensus protocols have been developed over time in the form of societal mechanisms to assess, weight, combine and isolate individual people opinions. In distributed machine learning environments however, individual AI agents are merely part of a system where decisions are made in a centralized and aggregated fashion or require a fixed network topology, a practice prone to security risks and collaboration is nearly absent. For instance, Byzantine Failures may tamper both
the training and inference stage of individual AI agents, leading to significantly reduced overall system performance. Inspired by societal practices, we propose a decentralized inference strategy where each individual agent is empowered to make their own decisions, by exchanging and aggregating information with other agents in their network. To this end, a ”Quality of Inference” consensus protocol (QoI) is proposed, forming a single commonly accepted inference rule applied by every individual agent. The overall system knowledge and decisions on specific manners can thereby be stored by all individual agents in a decentralized fashion, employing e.g., blockchain technology. Our experiments in classification tasks indicate that the proposed approach forms a secure decentralized inference framework, that prevents adversaries at tampering the overall process and achieves comparable performance with centralized decision aggregation methods
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