Investigation of Stepwise Charging Circuits for Power-Clock Generation in Adiabatic Logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits

Energy efficiency of 2- Step power-clocks for adiabatic logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parameters such as tank-capacitance to load capacitance ratio, ramping time, transistors sizing and power supply voltage scaling on energy recovery achievable in the 2-step charging circuit. We show that energy recovery achievable in the 2-step charging circuit depends on the tank-capacitor and load capacitor size concluding that tank-capacitance (CT) versus load capacitance (CL) is the significant parameter. We also show that the energy performance depends on the ramping time and improves for higher ramping times (lower frequencies). Energy recovery also improves if the transistors sizes in the step charging circuit are sized at their minimum dimensions. Lastly, we show that energy recovery decreases as the power supply voltage is scaled down. Specifically, the decrease in the energy recovery with decreasing power supply is significant for lower ramping times (higher frequencies). We propose that a Ct/Cl ratio of 10, keeping the width of the transistors in the step charging circuit minimum, can be chosen as a convenient `rule-of-thumb' in practical designs

A Study on Energy-Efficient Inductor Current Controls for Maximum Energy Delivery in Battery-free Buck Converter

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 김재하.A discontinuous conduction mode (DCM) buck converter, which acts as a voltage regulator in battery-free applications, is proposed to maximize the ener-gy delivery to the load system. In this work, we focus the energy loss problem during start-up and steady-state operation of the buck converter, which severely limits the energy delivery. Especially, the energy loss problem arises from the fact that there is no constant power source such as a battery and the only a small amount of energy harvested from the ambient energy sources is available. To address such energy loss problem, this dissertation proposes optimal induc-tor current control techniques at each operation to greatly reduce the energy losses. First, a switching-based stepwise capacitor charging scheme is presented that can charge the output capacitor with constant inductor current during start-up operation. By switching the inductor with gradually incrementing duty-cycle ratios in a stepwise fashion, the buck converter can make the inductor current a constant current source, which can greatly reduce the start-up energy loss com-pared to that in the conventional capacitor charging scheme with a voltage source. Second, a variable on-time (VOT) pulse-frequency-modulation (PFM) scheme is presented that can keep the peak inductor current constant during steady-state operation. By adaptively varying the on-time according to the op-erating voltage conditions of the buck converter, it can suppress the voltage ripple and improve the power efficiency even with a small output capacitor. Third, an adaptive off-time positioning zero-crossing detector (AOP-ZCD) is presented that can adaptively position the turn-off timing of the low-side switch close to the zero-inductor-current timing by predicting the inductor current waveform without using a power-hungry continuous-time ZCD. To demonstrate the proposed design concepts, the prototype battery-free wireless remote switch including the piezoelectric energy harvester and the proposed buck converter was fabricated in a 250 nm high-voltage CMOS technology. It can harvest a total energy of 246 μJ from a single button press action of a 300-mm2 lead magnesium niobate-lead titanate (PMN-PT) piezoelectric disc, and deliver more than 200 μJ to the load, which is sufficient to transmit a 4-byte-long message via 2.4-GHz wireless USB channel over a 10-m distance. If such battery-free application does not use the proposed buck converter, the energy losses in-curred at the buck converter would be larger than the energy harvested, and therefore it cannot operate with a single button-pressing action. Furthermore, thanks to the proposed energy efficient buck converter, the battery-free wire-less remote switch can be realized by using a cheaper PZT piezoelectric source, which can achieve a 10× cost reduction.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS CONTRIBUTION AND ORGANIZATION 6 CHAPTER 2 OPERATION MODE AND OVERALL ARCHITECTURE 8 2.1 TOPOLOGY SELECTION 8 2.2 PRINCIPLE OF OPERATION 11 2.2.1 BASIC OPERATION IN CCM 12 2.2.2 BASIC OPERATION IN DCM 15 2.3 OPERATION MODE 17 2.4 OVERALL ARCHITECTURE 19 CHAPTER 3 OPTIMAL INDUCTOR CURRENT CONTROLS FOR MAXIMUM ENERGY DELIVERY 23 3.1 CONSTANT INDUCTOR CURRENT CONTROL WITH SWITCHING-BASED STEPWISE CAPACITOR CHARGING SCHEME 24 3.1.1 CONVENTIONAL CHARGING SCHEME WITH A SWITCH 24 3.1.2 ADIABATIC STEPWISE CHARGING 27 3.1.3 PROPOSED START-UP SCHEME 29 3.2 CONSTANT INDUCTOR PEAK CURRENT CONTROL WITH VARIABLE ON-TIME PFM SCHEME 35 3.2.1 BASIC OPERATION OF PFM BUCK CONVERTER 35 3.2.2 CONSTANT ON-TIME PFM SCHEME 39 3.2.3 VARIABLE ON-TIME PFM SCHEME 41 3.3 INDUCTOR CURRENT PREDICTION WITH ADAP-TIVE OFF-TIME POSITIONING ZCD (AOP-ZCD) 44 3.3.1 PREVIOUS SAMPLING-BASED ZCD 44 3.3.2 PROPOSED ADAPTIVE OFF-TIME POSITIONING ZCD 47 CHAPTER 4 CIRCUIT IMPLEMENTATION 49 4.1 CIRCUIT IMPLEMENTATION OF SWITCHING-BASED STEPWISE CAPACITOR CHARGER 49 4.1.1 VOLTAGE DETECTOR (VD) 50 4.1.2 DIGITAL PULSE WIDTH MODULATOR (DPWM) 52 4.1.3 PROGRAMMABLE DUTY-CYCLE CONTROLLER (DCC) 55 4.1.4 SWITCHED CAPACITOR (SC) STEP-DOWN CONVERTER 57 4.2 CIRCUIT IMPLEMENTATION OF VARIABLE ON-TIME PULSE GENERATOR 59 4.3 CIRCUIT IMPLEMENTATION OF ADAPTIVE OFF-TIME POSITIONING ZCD 64 4.3.1 ADAPTIVE OFF-TIME (AOT) PULSE GENERATOR 64 4.3.2 TIMING ERROR DETECTOR AND SHIFT-REGISTER 68 CHAPTER 5 MEASUREMENT RESULTS OF PROPOSED BUCK CONVERTER 70 5.1 SWITCHING-BASED STEPWISE CAPACITOR CHARGER 71 5.2 STEADY-STATE PERFORMANCE WITH VOT PULSE GENERATOR AND AOP-ZCD 74 CHAPTER 6 REALIZATION OF BATTERY-FREE WIRELESS REMOTE SWITCH 84 6.1 KEY BUILDING BLOCKS OF BATTERY-FREE WIRELESS REMOTE SWITCH 85 6.2 PIEZOELECTRIC ENERGY HARVESTER WITH P-SSHI RECTIFIER 86 6.2.1 ANALYSIS ON SINGLE-PULSED ENERGY HARVESTING 88 6.2.2 PROPOSED PIEZOELECTRIC ENERGY HARVESTER 91 6.2.3 CIRCUIT IMPLEMENTATION 93 6.3 MEASUREMENT RESULTS OF BATTERY-FREE WIRELESS SWITCH 96 CHAPTER 7 CONCLUSION 101 BIBLIOGRAPHY 103 초 록 110Docto

Adiabatic Circuits for Power-Constrained Cryptographic Computations

This thesis tackles the need for ultra-low power operation in power-constrained cryptographic computations. An example of such an application could be smartcards. One of the techniques which has proven to have the potential of rendering ultra-low power operation is ‘Adiabatic Logic Technique’. However, the adiabatic circuits has associated challenges due to high energy dissipation of the Power-Clock Generator (PCG) and complexity of the multi-phase power-clocking scheme. Energy efficiency of the adiabatic system is often degraded due to the high energy dissipation of the PCG. In this thesis, nstep charging strategy using tank capacitors is considered for the power-clock generation and several design rules and trade-offs between the circuit complexity and energy efficiency of the PCG using n-step charging circuits have been proposed. Since pipelining is inherent in adiabatic logic design, careful selection of architecture is essential, as otherwise overhead in terms of area and energy due to synchronization buffers is induced specifically, in the case of adiabatic designs using 4-phase power-clocking scheme. Several architectures for the Montgomery multiplier using adiabatic logic technique are implemented and compared. An architecture which constitutes an appropriate trade-off between energy efficiency and throughput is proposed along with its methodology. Also, a strategy to reduce the overhead due to synchronization buffers is proposed. A modification in the Montgomery multiplication algorithm is proposed. Furthermore, a problem due to the application of power-clock gating in cascade stages of adiabatic logic is identified. The problem degrades the energy savings that would otherwise be obtained by the application of power-clock gating. A solution to this problem is proposed. Cryptographic implementations also present an obvious target for Power Analysis Attacks (PAA). There are several existing secure adiabatic logic designs which are proposed as a countermeasure against PAA. Shortcomings of the existing logic designs are identified, and two novel secure adiabatic logic designs are proposed as the countermeasures against PAA and improvement over the existing logic designs

Asynchrobatic logic for low-power VLSI design

In this work, Asynchrobatic Logic is presented. It is a novel low-power design style that combines the energy saving benefits of asynchronous logic and adiabatic logic to produce systems whose power dissipation is reduced in several different ways. The term “Asynchrobatic” is a new word that can be used to describe these types of systems, and is derived from the concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis introduces the concept and theory behind Asynchrobatic Logic. It first provides an introductory background to both underlying parent technologies (asynchronous logic and adiabatic logic). The background material continues with an explanation of a number of possible methods for designing complex data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then introduced as a comparison between asynchronous and Asynchrobatic buffer chains, showing that for wide systems, it operates more efficiently. Two more-complex sub-systems are presented, firstly a layout implementation of the substitution boxes from the Twofish encryption algorithm, and secondly a front-end only (without parasitic capacitances, resistances) simulation that demonstrates a functional system capable of calculating the Greatest Common Denominator (GCD) of a pair of 16-bit unsigned integers, which under typical conditions on a 0.35μm process, executed a test vector requiring twenty-four iterations in 2.067μs with a power consumption of 3.257nW. These examples show that the concept of Asynchrobatic Logic has the potential to be used in real-world applications, and is not just theory without application. At the time of its first publication in 2004, Asynchrobatic Logic was both unique and ground-breaking, as this was the first time that consideration had been given to operating large-scale adiabatic logic in an asynchronous fashion, and the first time that Asynchronous Stepwise Charging (ASWC) had been used to drive an adiabatic data-path

Low power predictable memory and processing architectures

Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

Electrocaloric coolers and pyroelectric energy harvesters based on multilayer capacitors of Pb(Sc0.5Ta0.5)O3

The following work investigates the development of heat pumps that exploit electrocaloric effects in Pb(Sc,Ta)03 (PST) multilayer capacitors (MLCs). The electrocaloric effect refers to reversible thermal changes in a material upon application (and removal) of an electric field. Electrocaloric cooling is interesting because 1) it has the potential to be more efficient than competing technologies, such as vapour-compression systems, and 2) it does not compel the use of greenhouse gases, which is crucial in order to slow down global warming and mitigate the effects of climate change. The continuous progress in the field of electrocalorics has promoted the creation of several electrocaloric based heat pump prototypes. Despite the different designs and working principles utilized, these prototypes have struggled to maintain temperature variations as large as 10 K, discouraging their industrial development. In this work, bespoke PST-MLCs exhibiting large electrocaloric effects near room temperature were embodied in a novel heat pump with the motivation to surpass the 10 K-barrier. The experimental design of the heat pump was based on the outcome of a numerical model. After implementing some of the modifications suggested by the latter, consistent temperature spans of 13 K at 30 °C were reported, with cooling powers of 12 W / kg. Additional simulations predicted temperature spans as large as 50 K and cooling powers in the order of 1000 W / kg, if a new set of plausible modifications were to be put in place. Similarly, these very same PST-MLCs samples were implemented into pyroelectric harvesters revisiting Olsen's pioneering work from 1980. The harvested energies were found to be as large as 11.2 J, with energy densities reaching up to 4.4 J / cm3 of active material, when undergoing temperature oscillations of 100 K under electric fields applied of 140-200 kV / cm. These findings are two and four times, respectively, larger than the best reported values in the literature. The results obtained in this dissertation are beyond the state-of-the-art and show that 1) electrocaloric heat pumps can indeed achieve temperature spans larger than 10 K, and 2) pyroelectric harvesters can generate electrical energy in the Joule-range. Moreover, numerical models indicated that there is still room for improvement, especially when it comes to the power of these devices. This should encourage the development of these kinds of electrocaloric- and pyroelectric-based applications in the near future

Calculations and experiments on y-type Stirling engines.

This thesis is written to give an overview of the most important types of calculation methods for the analysis of y-type Stirling engines found in the last 60 years. Simple methods like the ideal process calculation and the 0th order analysis found by Beale and West are given to describe the process steps and to get a first reference value of performance and efficiency. Higher order calculations like the Schmidt analysis (1st order) and 2nd order methods for the ideal adiabatic and quasi steady flow models are described in detail and optimised for the y-type Stirling engine. With a generated quasi steady computer program code parameter variation is used to obtain an impression of the dependency of performance and efficiency on varying geometry data and boundary conditions. In addition to these models the heat exchanger sections heater, cooler and regenerator are analysed in depth with the CFD program ANSYS CFX. To compare the results of the theoretical analysis to measured ones three experimental engines are used. Different process values are determined on a biomass fired CHP Stirling system and on a solar Dish / Stirling system. On a Stirling engine test bench some of the parameter variations of the quasi steady program are repeated in experiments for comparison. These engines are modified in ways to make them run properly and to improve durability. The behaviour of the y-type Stirling engine is analysed in detail both in experiments and theoretically: this is felt to be unique. With the modified quasi steady flow model a method is found that is able to predict the process performance with a higher accuracy than it can be done with any other calculation method. This method can easily be modified to fit any other type of Stirling engine