Analysis of high capacity short reach optical links

Over the last few years, the global Internet traffic has grown exponentially due to the advent of the social networks, high definition streaming, online gaming, high performance computing and cloud services. The network is saturating, facing a challenge to provide enough capacity to such ever-demanding bandwidth expensive applications. Fiber optic communications is the only technology capable of dealing such high demands due to its advantages over the traditional electrical transmission technology. The short haul transmissions currently rely on direct detection due to low cost, low power and low complexity as compared to the coherent detection schemes. In order to increase the bit rate, several advance modulation formats are under investigation for short reach transmissions. Such links mostly use intensity modulation direct detection (IMDD) schemes providing a simple system when compared with the coherent receivers. In this thesis the performance of Multilevel Pulse Amplitude Modulation (MPAM) is studied using IMDD, providing good spectral efficiency as well as able to deal with the limited electronic devices bandwidth. MPAM can address the typical optical channel without the need to go with more complex and higher power modulation schemes. It provides a trade off between sensitivity and the complexity. So a simple communication system using MPAM is implemented using an external modulated laser transmitted over a distance of 2 km. In order to reduce the cost, single laser and single receiver technique is being adopted. The performance of the MPAM system in a bandwidth limited scenarios is studied with a possibility to use equalization techniques to improve the sensitivity. The utility of Forward Error Correction codes is also studied to improve the performance without increasing the latency. By increasing the number of bits per symbol, the system becomes more sensitive to the impairments. Moreover, the components and the connectors in the transmission system also introduces multipath interference (MPI) that is a key limitation to the use of advance modulation formats. Hence a detailed study is carried out to investigate the MPI effects. At the end, a novel idea based on reflective Mach-Zehnder modulator (MZM) is presented that reuses the modulated wavelength eliminating the need for a laser. As a consequent, the cost and power consumption specifically targeted for the optical interconnect environment is reduced. In a nutshell, the thesis provides an overview of the direct detection system targeted to the short optical links. It includes the studies related to the optical transmission systems and provides an insight of the available advance modulation formats and the detection schemes. Finally, the simulations and laboratory results are provided showing that adoption of MPAM is a viable solution that should be employed in high capacity short reach optical links

Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications

The rapid proliferation of the Internet has been driving communication networks closer and closer to their limits, while available bandwidth is disappearing due to an ever-increasing network load. Over the past decade, optical fiber communication technology has increased per fiber data rate from 10 Tb/s to exceeding 10 Pb/s. The major explosion came after the maturity of coherent detection and advanced digital signal processing (DSP). DSP has played a critical role in accommodating channel impairments mitigation, enabling advanced modulation formats for spectral efficiency transmission and realizing flexible bandwidth. This book aims to explore novel, advanced DSP techniques to enable multi-Tb/s/channel optical transmission to address pressing bandwidth and power-efficiency demands. It provides state-of-the-art advances and future perspectives of DSP as well

Novel load identification techniques and a steady state self-tuning prototype for switching mode power supplies

Control of Switched Mode Power Supplies (SMPS) has been traditionally achieved through analog means with dedicated integrated circuits (ICs). However, as power systems are becoming increasingly complex, the classical concept of control has gradually evolved into the more general problem of power management, demanding functionalities that are hardly achievable in analog controllers. The high flexibility offered by digital controllers and their capability to implement sophisticated control strategies, together with the programmability of controller parameters, make digital control very attractive as an option for improving the features of dcdc converters. On the other side, digital controllers find their major weak point in the achievable dynamic performances of the closed loop system. Indeed, analogto-digital conversion times, computational delays and sampling-related delays strongly limit the small signal closed loop bandwidth of a digitally controlled SMPS. Quantization effects set other severe constraints not known to analog solutions. For these reasons, intensive scientific research activity is addressing the problem of making digital compensator stronger competitors against their analog counterparts in terms of achievable performances. In a wide range of applications, dcdc converters with high efficiency over the whole range of their load values are required. Integrated digital controllers for Switching Mode Power Supplies are gaining growing interest, since it has been shown the feasibility of digital controller ICs specifically developed for high frequency switching converters. One very interesting potential benefit is the use of autotuning of controller parameters (on-line controllers), so that the dynamic response can be set at the software level, independently of output capacitor filters, component variations and ageing. These kind of algorithms are able to identify the output filter configuration (system identification) and then automatically compute the best compensator gains to adjust system margins and bandwidth. In order to be an interesting solution, however, the self-tuning should satisfy two important requirements: it should not heavily affect converter operation under nominal condition and it should be based on a simple and robust algorithm whose complexity does not require a significant increase of the silicon area of the IC controller. The first issue is avoided performing the system identification (SI) with the system open loop configuration, where perturbations can be induced in the system before the start up. Much more challenging is to satisfy this requirement during steady state operations, where perturbations on the output voltage are limited by the regular operations of the converter. The main advantage of steady state SI methods, is the detection of possible non-idealities occurring during the converter operations. In this way, the system dynamics can be consequently adjusted with the compensator parameters tuning. The resource saving issue, requires the development of äd-hocßelf-tuning techniques specifically tailored for integrated digitally controlled converters. Considering the flexibility of digital control, self-tuning algorithms can be studied and easily integrated at hardware level into closed loop SMPS reducing development time and R & D costs. The work of this dissertation finds its origin in this context. Smart power management is accomplished by tuning the controller parameters accordingly to the identified converter configuration. Themain difficult for self-tuning techniques is the identification of the converter output filter configuration. Two novel system identification techniques have been validated in this dissertation. The open loop SI method is based on the system step response, while dithering amplification effects are exploited for the steady state SI method. The open loop method can be used as autotunig approach during or before the system start up, a step evolving reference voltage has been used as system perturbation and to obtain the output filter information with the Power Spectral Density (PSD) computation of the system step response. The use of ¢§ modulator is largely increasing in digital control feedback. During the steady state, the finite resolution introduces quantization effects on the signal path causing low frequency contributes of the digital control word. Through oversampling-dithering capabilities of ¢§ modulators, resolution improvements are obtained. The presented steady state identification techniques demonstrates that, amplifying the dithering effects on the signal path, the output filter information can be obtained on the digital side by processing with the PSD computation the perturbed output voltage. The amount of noise added on the output voltage does not affect the converter operations, mathematical considerations have been addressed and then justified both with a Matlab/Simulink fixed-point and a FPGA-based closed loop system. The load output filter identification of both algorithms, refer to the frequency domain. When the respective perturbations occurs, the system response is observed on the digital side and processed with the PSD computation. The extracted parameters are the resonant frequency ans the possible ESR (Effective Series Resistance) contributes,which can be detected as maximumin the PSD output. The SI methods have been validated for different configurations of buck converters on a fixed-point closed loop model, however, they can be easily applied to further converter configurations. The steady state method has been successfully integrated into a FPGA-based prototype for digitally controlled buck converters, that integrates a PSD computer needed for the load parameters identification. At this purpose, a novel VHDL-coded full-scalable hybrid processor for Constant Geometry FFT (CG-FFT) computation has been designed and integrated into the PSD computation system. The processor is based on a variation of the conventional algorithm used for FFT, which is the Constant-Geometry FFT (CG-FFT).Hybrid CORDIC-LUT scalable architectures, has been introduced as alternative approach for the twiddle factors (phase factors) computation needed during the FFT algorithms execution. The shared core architecture uses a single phase rotator to satisfy all TF requests. It can achieve improved logic saving by trading off with computational speed. The pipelined architecture is composed of a number of stages equal to the number of PEs and achieves the highest possible throughput, at the expense of more hardware usage

Novel load identification techniques and a steady state self-tuning prototype for switching mode power supplies

Control of Switched Mode Power Supplies (SMPS) has been traditionally achieved through analog means with dedicated integrated circuits (ICs). However, as power systems are becoming increasingly complex, the classical concept of control has gradually evolved into the more general problem of power management, demanding functionalities that are hardly achievable in analog controllers. The high flexibility offered by digital controllers and their capability to implement sophisticated control strategies, together with the programmability of controller parameters, make digital control very attractive as an option for improving the features of dcdc converters. On the other side, digital controllers find their major weak point in the achievable dynamic performances of the closed loop system. Indeed, analogto-digital conversion times, computational delays and sampling-related delays strongly limit the small signal closed loop bandwidth of a digitally controlled SMPS. Quantization effects set other severe constraints not known to analog solutions. For these reasons, intensive scientific research activity is addressing the problem of making digital compensator stronger competitors against their analog counterparts in terms of achievable performances. In a wide range of applications, dcdc converters with high efficiency over the whole range of their load values are required. Integrated digital controllers for Switching Mode Power Supplies are gaining growing interest, since it has been shown the feasibility of digital controller ICs specifically developed for high frequency switching converters. One very interesting potential benefit is the use of autotuning of controller parameters (on-line controllers), so that the dynamic response can be set at the software level, independently of output capacitor filters, component variations and ageing. These kind of algorithms are able to identify the output filter configuration (system identification) and then automatically compute the best compensator gains to adjust system margins and bandwidth. In order to be an interesting solution, however, the self-tuning should satisfy two important requirements: it should not heavily affect converter operation under nominal condition and it should be based on a simple and robust algorithm whose complexity does not require a significant increase of the silicon area of the IC controller. The first issue is avoided performing the system identification (SI) with the system open loop configuration, where perturbations can be induced in the system before the start up. Much more challenging is to satisfy this requirement during steady state operations, where perturbations on the output voltage are limited by the regular operations of the converter. The main advantage of steady state SI methods, is the detection of possible non-idealities occurring during the converter operations. In this way, the system dynamics can be consequently adjusted with the compensator parameters tuning. The resource saving issue, requires the development of äd-hocßelf-tuning techniques specifically tailored for integrated digitally controlled converters. Considering the flexibility of digital control, self-tuning algorithms can be studied and easily integrated at hardware level into closed loop SMPS reducing development time and R & D costs. The work of this dissertation finds its origin in this context. Smart power management is accomplished by tuning the controller parameters accordingly to the identified converter configuration. Themain difficult for self-tuning techniques is the identification of the converter output filter configuration. Two novel system identification techniques have been validated in this dissertation. The open loop SI method is based on the system step response, while dithering amplification effects are exploited for the steady state SI method. The open loop method can be used as autotunig approach during or before the system start up, a step evolving reference voltage has been used as system perturbation and to obtain the output filter information with the Power Spectral Density (PSD) computation of the system step response. The use of ¢§ modulator is largely increasing in digital control feedback. During the steady state, the finite resolution introduces quantization effects on the signal path causing low frequency contributes of the digital control word. Through oversampling-dithering capabilities of ¢§ modulators, resolution improvements are obtained. The presented steady state identification techniques demonstrates that, amplifying the dithering effects on the signal path, the output filter information can be obtained on the digital side by processing with the PSD computation the perturbed output voltage. The amount of noise added on the output voltage does not affect the converter operations, mathematical considerations have been addressed and then justified both with a Matlab/Simulink fixed-point and a FPGA-based closed loop system. The load output filter identification of both algorithms, refer to the frequency domain. When the respective perturbations occurs, the system response is observed on the digital side and processed with the PSD computation. The extracted parameters are the resonant frequency ans the possible ESR (Effective Series Resistance) contributes,which can be detected as maximumin the PSD output. The SI methods have been validated for different configurations of buck converters on a fixed-point closed loop model, however, they can be easily applied to further converter configurations. The steady state method has been successfully integrated into a FPGA-based prototype for digitally controlled buck converters, that integrates a PSD computer needed for the load parameters identification. At this purpose, a novel VHDL-coded full-scalable hybrid processor for Constant Geometry FFT (CG-FFT) computation has been designed and integrated into the PSD computation system. The processor is based on a variation of the conventional algorithm used for FFT, which is the Constant-Geometry FFT (CG-FFT).Hybrid CORDIC-LUT scalable architectures, has been introduced as alternative approach for the twiddle factors (phase factors) computation needed during the FFT algorithms execution. The shared core architecture uses a single phase rotator to satisfy all TF requests. It can achieve improved logic saving by trading off with computational speed. The pipelined architecture is composed of a number of stages equal to the number of PEs and achieves the highest possible throughput, at the expense of more hardware usage

Direct digital synthesizers : theory, design and applications

Traditional designs of high bandwidth frequency synthesizers employ the use of a phase-locked-loop (PLL). A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. Fast settling time, sub-Hertz frequency resolution, continuous-phase switching response and low phase noise are features easily obtainable in the DDS systems. Although the principle of the DDS has been known for many years, the DDS did not play a dominant role in wideband frequency generation until recent years. Earlier DDSs were limited to produce narrow bands of closely spaced frequencies, due to limitations of digital logic and D/A-converter technologies. Recent advantages in integrated circuit (IC) technologies have brought about remarkable progress in this area. By programming the DDS, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. This is an important step towards a "software-radio" which can be used in various systems. The DDS could be applied in the modulator or demodulator in the communication systems. The applications of DDS are restricted to the modulator in the base station. The aim of this research was to find an optimal front-end for a transmitter by focusing on the circuit implementations of the DDS, but the research also includes the interface to baseband circuitry and system level design aspects of digital communication systems. The theoretical analysis gives an overview of the functioning of DDS, especially with respect to noise and spurs. Different spur reduction techniques are studied in detail. Four ICs, which were the circuit implementations of the DDS, were designed. One programmable logic device implementation of the CORDIC based quadrature amplitude modulation (QAM) modulator was designed with a separate D/A converter IC. For the realization of these designs some new building blocks, e.g. a new tunable error feedback structure and a novel and more cost-effective digital power ramp generator, were developed.reviewe

Fast Fourier transforms on energy-efficient application-specific processors

Many of the current applications used in battery powered devices are from digital signal processing, telecommunication, and multimedia domains. Traditionally application-specific fixed-function circuits have been used in these designs in form of application-specific integrated circuits (ASIC) to reach the required performance and energy-efficiency. The complexity of these applications has increased over the years, thus the design complexity has increased even faster, which implies increased design time. At the same time, there are more and more standards to be supported, thus using optimised fixed-function implementations for all the functions in all the standards is impractical. The non-recurring engineering costs for integrated circuits have also increased significantly, so manufacturers can only afford fewer chip iterations. Although tailoring the circuit for a specific application provides the best performance and/or energy-efficiency, such approach lacks flexibility. E.g., if an error is found after the manufacturing, an expensive chip iteration is required. In addition, new functionalities cannot be added afterwards to support evolution of standards. Flexibility can be obtained with software based implementation technologies. Unfortunately, general-purpose processors do not provide the energy-efficiency of the fixed-function circuit designs. A useful trade-off between flexibility and performance is implementation based on application-specific processors (ASP) where programmability provides the flexibility and computational resources customised for the given application provide the performance. In this Thesis, application-specific processors are considered by using fast Fourier transform as the representative algorithm. The architectural template used here is transport triggered architecture (TTA) which resembles very long instruction word machines but the operand execution resembles data flow machines rather than traditional operand triggering. The developed TTA processors exploit inherent parallelism of the application. In addition, several characteristics of the application have been identified and those are exploited by developing customised functional units for speeding up the execution. Several customisations are proposed for the data path of the processor but it is also important to match the memory bandwidth to the computation speed. This calls for a memory organisation supporting parallel memory accesses. The proposed optimisations have been used to improve the energy-efficiency of the processor and experiments show that a programmable solution can have energy-efficiency comparable to fixed-function ASIC designs

Tecnologias coerentes para redes ópticas flexíveis

Next-generation networks enable a broad range of innovative services with the best delivery by utilizing very dense wired/wireless networks. However, the development of future networks will require several breakthroughs in optical networks such as high-performance optical transceivers to support a very-high capacity optical network as well as optimization of the network concept, ensuring a dramatic reduction of the cost per bit. At the same time, all of the optical network segments (metro, access, long-haul) need new technology options to support high capacity, spectral efficiency and data-rate flexibility. Coherent detection offers an opportunity by providing very high sensitivity and supporting high spectral efficiency. Coherent technology can still be combined with polarization multiplexing. Despite the increased cost and complexity, the migration to dual-polarization coherent transceivers must be considered, as it enables to double the spectral efficiency. These dual-polarization systems require an additional digital signal processing (DSP) subsystem for polarization demultiplexing. This work seeks to provide and characterize cost-effective novel coherent transceivers for the development of new generation practical, flexible and high capacity transceivers for optical metro-access and data center interconnects. In this regard, different polarization demultiplexing (PolDemux) algorithms, as well as adaptive Stokes will be considered. Furthermore, low complexity and modulation format-agnostic DSP techniques based on adaptive Stokes PolDemux for flexible and customizable optical coherent systems will be proposed. On this subject, the performance of the adaptive Stokes algorithm in an ultra-dense wavelength division multiplexing (U-DWDM) system will be experimentally evaluated, in offline and real-time operations over a hybrid optical-wireless link. In addition, the efficiency of this PolDemux algorithm in a flexible optical metro link based on Nyquist pulse shaping U-DWDM system and hybrid optical signals will be assessed. Moreover, it is of great importance to find a transmission technology that enables to apply the Stokes PolDemux for long-haul transmission systems and data center interconnects. In this work, it is also proposed a solution based on the use of digital multi-subcarrier multiplexing, which improve the performance of long-haul optical systems, without increasing substantially, their complexity and cost.As redes de telecomunicações futuras permitirão uma ampla gama de serviços inovadores e com melhor desempenho. No entanto, o desenvolvimento das futuras redes implicará vários avanços nas redes de fibra ótica, como transcetores óticos de alto desempenho capazes de suportar ligações de muito elevada capacidade, e a otimização da estrutura da rede, permitindo uma redução drástica do custo por bit transportado. Simultaneamente, todos os segmentos de rede ótica (metropolitanas, acesso e longo alcance) necessitam de novas opções tecnológicas para suportar uma maior capacidade, maior eficiência espetral e flexibilidade. Neste contexto, a deteção coerente surge como uma oportunidade, fornecendo alta sensibilidade e elevada eficiência espetral. A tecnologia de deteção coerente pode ainda ser associada à multiplexação na polarização. Apesar de um potencial aumento ao nível do custo e da complexidade, a migração para transcetores coerentes de dupla polarização deve ser ponderada, pois permite duplicar a eficiência espetral. Esses sistemas de dupla polarização requerem um subsistema de processamento digital de sinal (DSP) adicional para desmultiplexagem da polarização. Este trabalho procura fornecer e caracterizar novos transcetores coerentes de baixo custo para o desenvolvimento de uma nova geração de transcetores mais práticos, flexíveis e de elevada capacidade, para interconexões óticas ao nível das futuras redes de acesso e metro. Assim, serão analisados diferentes algoritmos para a desmultiplexagem da polarização, incluindo uma abordagem adaptativa baseada no espaço de Stokes. Além disso, são propostas técnicas de DSP independentes do formato de modulação e de baixa complexidade baseadas na desmultiplexagem de Stokes adaptativa para sistemas óticos coerentes flexíveis. Neste contexto, o desempenho do algoritmo adaptativo de desmultiplexagem na polarização baseado no espaço de Stokes é avaliado experimentalmente num sistema U-DWDM, tanto em análises off-line como em tempo real, considerando um percurso ótico hibrido que combina um sistema de transmissão suportado por fibra e outro em espaço livre. Foi ainda analisada a eficiência do algoritmo de desmultiplexagem na polarização numa rede ótica de acesso flexível U-DWDM com formatação de pulso do tipo Nyquist. Neste trabalho foi ainda analisada a aplicação da técnica de desmultiplexagem na polarização baseada no espaço de Stokes para sistemas de longo alcance. Assim, foi proposta uma solução de aplicação baseada no uso da multiplexagem digital de múltiplas sub-portadoras, tendo-se demonstrado uma melhoria na eficiência do desempenho dos sistemas óticos de longo alcance, sem aumentar significativamente a respetiva complexidade e custo.Programa Doutoral em Engenharia Eletrotécnic