Error Compensation in Pipeline and Converters

This thesis provides an improved calibration and compensation scheme for pipeline Analog-to-Digital Converters (ADCs). This new scheme utilizes the intermediate stage outputs in a pipeline to characterize error mechanisms in the architecture. The goal of this compensation scheme is to increase the dynamic range of the ADC. The pipeline architecture is described in general, and tailored to the 1.5 bitslstage topology. Dominant error mechanisms are defined and characterized for an arbitrary stage in the pipeline. These error mechanisms are modeled with basis functions. The traditional calibration scheme is modified and used to iteratively calculate the error characteristics. The information from calibration is used to compensate the ADC. The calibration and compensation scheme is demonstrated both in simulation and using a custom hardware pipeline ADC. A 10-bit 5 MHz ADC was designed and fabricated in 0.5 pm CMOS to serve as the demonstration platform. The scheme was successful in showing improvements in dynamic range while using intermediate stage outputs to efficiently model errors in a pipeline stage. An application of the technique on the real converter showed an average of 8.6 dB improvement in SFDR in the full Nyquist band of the ADC. The average improvement in SINAD and ENOB are 3.2 dB and 0.53 bits respectively

Nonlinear Switched-Capacitor Networks: Basic Principles and Piecewise-Linear Design

The applicability of switched-capacitor (SC) components to the design of nonlinear networks is extensively discussed in this paper. The main objective is to show that SC's can be efficiently used for designing nonlinear networks. Moreover, the design methods to be proposed here are fully compatible with general synthesis methods for nonlinear n -ports. Different circuit alternatives are given and their potentials are evaluated.Office of Naval Research (USA) N00014-76-C-0572Comisión Interministerial de Ciencia y Tecnología 0235/81Semiconductor Research Corporation (USA) 82-11-00

Epälineaarinen vääristymä laajakaistaisissa analogia-digitaalimuuntimissa

This thesis discusses nonlinearities of analog-to-digital converters (ADCs) and their mitigation using digital signal processing (DSP). Particularly wideband radio receivers are considered here including, e.g., the emerging cognitive radio applications. In this kind of receivers, a single ADC converts a mixture of signals at different frequency bands to digital domain simultaneously. Different signals may have considerably different power levels and hence the overall dynamic range can be very large (even 50–60 dB). Therefore, even the smallest ADC nonlinearities can produce considerable amount of nonlinear distortion, which may cause a strong signal to block significantly weaker signal bands. One concrete source of nonlinear distortion is waveform clipping due to improper signal conditioning in the input of an ADC. In the thesis, a mathematical model for this phenomenon is derived through Fourier analysis and is then used as a basis for an adaptive interference cancellation (AIC) method. This is a general method for reducing nonlinear distortion and besides clipping it can be used, e.g., to compensate integral nonlinearity (INL) originating from unintentional deviations of the quantization levels. Additionally, an interpolation method is proposed in this thesis to restore clipped waveforms and hence reduce nonlinear distortion. Through several computer simulations and corresponding laboratory radio signal measurements, the performance of the proposed post-processing methods is illustrated. It can be seen from the results that the methods are able to reduce nonlinear distortion from a weak signal band in a considerable manner when there are strong blocking signals in the neighboring channels. According to the results, the AIC method would be a highly recommendable post-processing technique for modern radio receivers due to its general ability to reduce nonlinear distortion regardless of its source. /Kir10Tässä työssä käsitellään analogia-digitaalimuuntimien (AD-muuntimien) epälineaarisuuksia ja niiden lieventämistä digitaalisen signaalinkäsittelyn (DSP) avulla. Tätä on tarkasteltu erityisesti laajakaistaisten radiovastaanottimien näkökulmasta, joka käsittää mm. tulevat kognitiiviseen radioon liittyvät sovellukset. Tällaisissa vastaanottimissa yksittäinen AD-muunnin muuntaa samanaikaisesti useita eri taajuuskaistoilla olevia signaaleita digitaaliseen muotoon, jolloin yhteenlaskettu dynaaminen alue voi olla hyvin suuri (jopa 50–60 dB). Tämän takia AD-muuntimen pienimmätkin epälineaarisuudet voivat aiheuttaa huomattavasti epälineaarista vääristymää, minkä vuoksi voimakas signaali saattaa häiriöllään peittää muilla taajuuskaistoilla olevia selkeästi heikompia signaaleja. Eräs konkreettinen epälineaarisen vääristymän aiheuttaja on aaltomuodon leikkaantuminen AD-muuntimen sisäänmenossa jännitealueen ylittymisen vuoksi. Tässä työssä johdetaan matemaattinen malli kyseiselle ilmiölle Fourier-analyysin avulla ja käytetään sitä lähtökohtana adaptiiviselle häiriönpoistomenetelmälle (AIC-menetelmä). Se on yleisluonteinen menetelmä epälineaarisen vääristymän vähentämiseksi, ja leikkaantumisen lisäksi sitä voidaan käyttää esimerkiksi kompensoimaan integraalista epälineaarisuutta (INL), joka on peräisin kvantisointitasojen tahattomista poikkeamista. Lisäksi tässä työssä esitellään interpolointimenetelmä leikkaantuneen aaltomuodon ehostamiseen siten, että epälineaarinen häiriö vähenee. Esiteltyjen jälkikäsittelymenetelmien suorituskykyä analysoidaan ja havainnollistetaan useilla tietokonesimulaatiolla sekä niitä vastaavilla radiosignaalien laboratoriomittauksilla. Tuloksista voidaan nähdä, että nämä menetelmät kykenevät poistamaan huomattavasti epälineaarista vääristymää heikolta signaalikaistalta silloin, kun naapurikaistoilla on voimakkaita häiriösignaaleja. Tulosten perusteella AIC-menetelmä olisi erittäin suositeltava jälkikäsittelytekniikka moderneihin radiovastaanottimiin, koska se pystyy yleisesti vähentämään epälineaarista vääristymää riippumatta häiriön alkuperästä

Digital Pulse Width Modulator Techniques For Dc - Dc Converters

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit

Digital electronic predistortion for optical communications

The distortion of optical signals has long been an issue limiting the performance of communication systems. With the increase of transmission speeds the effects of distortion are becoming more prominent. Because of this, the use of methods known from digital signal processing (DSP) are being introduced to compensate for them. Applying DSP to improve optical signals has been limited by a discrepancy in digital signal processing speeds and optical transmission speeds. However high speed Field Programmable Gate Arrays (FPGA) which are sufficiently fast have now become available making DSP experiments without costly ASIC implementation possible for optical transmission experiments. This thesis focuses on Look Up Table (LUT) based digital Electronic Predistortion (EPD) for optical transmission. Because it is only one out of many possible implementations of EPD, it has to be placed in context with other EPD techniques and other distortion combating techniques in general, especially since it is possible to combine the different techniques. Building an actual transmitter means that compromises and decisions have to be made in the design and implementation of an EPD based system. These are based on balancing the desire to achieve optimal performance with technological and economic limitations. This is partly done using optical simulations to asses the performance. This thesis describes a novel experimental transmitter that has been built as part of this research applying LUT based EPD to an optical signal. The experimental transmitter consists of a digital design (using a hardware description language) for a pair of FPGAs and an analogue optical/electronic setup including two standard DAC integrated circuits. The DSP in the transmitter compensated for both chromatic dispersion and self phase modulation. We achieved transmission of 10.7 Gb/s non-return-to-zero (NRZ) signals with a +4 dBm launch power over 450 km keeping the required optical-signal-to-noise-ratio (OSNR) for a bit-error-rate of 2x10^{-3} below 11 dB. In doing so we showed experimentally, for the first time, that nonlinear effects can be compensated with this approach and that the combination of FPGA-DAC is a viable approach for an experimental setup

A pipelined baseband digital predistortion architecture for RF amplifier linearization

This thesis describes the design of a baseband digital predistortion architecture for radio frequency (RF) amplifier linearization. Existing amplifier linearization techniques are first examined. The nonlinearity of an amplifier can be characterized as amplitude-to-amplitude distortion and amplitude-to-phase distortion. The distortion can be corrected by providing a predistorted driver signal (both in amplitude and phase) to the amplifier. This counteracts the nonlinearity of the amplifier so that the overall system is more linear. A pipelined predistortion architecture is designed to allow fast processing speed, and is capable of providing linearization for a bandwidth of 25 Mhz. The simulation results show significant improvement in amplifier's performance using predistortion technique. The system bandwidth versus cost is examined by using commercially available components

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied

Measurements, Models, Systems and Design

531 s.

Inertial orientation tracker having gradual automatic drift compensation for tracking human head and other similarly sized body

A self contained sensor apparatus generates a signal that corresponds to at least two of the three orientational aspects of yaw, pitch and roll of a human-scale body, relative to an external reference frame. A sensor generates first sensor signals that correspond to rotational accelerations or rates of the body about certain body axes. The sensor may be mounted to the body. Coupled to the sensor is a signal processor for generating orientation signals relative to the external reference frame that correspond to the angular rate or acceleration signals. The first sensor signals are impervious to interference from electromagnetic, acoustic, optical and mechanical sources. The sensors may be rate sensors. An integrator may integrate the rate signal over time. A drift compensator is coupled to the rate sensors and the integrator. The drift compensator may include a gravitational tilt sensor or a magnetic field sensor or both. A verifier periodically measures the orientation of the body by a means different from the drift sensitive rate sensors. The verifier may take into account characteristic features of human motion, such as stillness periods. The drift compensator may be, in part, a Kalman filter, which may utilize statistical data about human head motion

inertial orientation tracker having automatic drift compensation using an at rest sensor for tracking parts of a human body

A self contained sensor apparatus generates a signal that corresponds to at least two of the three orientational aspects of yaw, pitch and roll of a human-scale body, relative to an external reference frame. A sensor generates first sensor signals that correspond to rotational accelerations or rates of the body about certain body axes. The sensor may be mounted to the body. Coupled to the sensor is a signal processor for generating orientation signals relative to the external reference frame that correspond to the angular rate or acceleration signals. The first sensor signals are impervious to interference from electromagnetic, acoustic, optical and mechanical sources. The sensors may be rate sensors. An integrator may integrate the rate signal over time. A drift compensator is coupled to the rate sensors and the integrator. The drift compensator may include a gravitational tilt sensor or a magnetic field sensor or both. A verifier periodically measures the orientation of the body by a means different from the drift sensitive sate sensors. The verifier may take into account characteristic features of human motion, such as stillness periods. The drift compensator may be, in part, a Kalman filter, which may utilize statistical data about human head motion