Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric

Oxide bypassed power MOSFET devices

Master'sMASTER OF ENGINEERIN

High Performance Low Voltage Power Mosfet For High-frequency Synchronous Buck Converters

Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with iv its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35µm process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power v Block incorporating these new device techniques is demonstrated with an excellent efficiency observed

Optimization of power MOSFET devices suitable for integrated circuits

Táto doktorská práca sa zaoberá návrhom laterálnych výkonových tranzistorov s nízkym špecifickým odporom pri zapnutom stave, vhodných pre integráciu do Integrovaných Obvodov.This doctoral thesis deals with the design of lateral power transistor with lower specific on-resistance for integration into IC.The new model of MOSFET with waffle gate pattern is there described. For first, time the conformal transformation the Schwarz-Christoffel mapping has been used for the description of nonhomogeneous current distribution in the channel area of MOSFET with waffle gate pattern. In addition base on the figure of merit definition Area Increment (AI) the topological theoretical limit of MOSFET with waffle gate pattern has been a first time defined

CMOS MESFET Cascode Amplifiers for RFIC Applications

abstract: There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

High Efficiency Microwave Amplifiers and SiC Varactors Optimized for Dynamic Load Modulation

The increasing use of mobile networks as the main source of internet connectivity is creating challenges in the infrastructure. Customer demand is a moving target and continuous hardware developments are necessary to supply higher data rates in an environmentally sustainable and cost effective way. This thesis reviews and advances the status of realizing wideband and high efficiency power amplifiers, which will facilitate improvements in network capacity and energy efficiency. Several demonstrator PAs are proposed, analyzed, designed, and characterized: First, resistive loading at higher harmonics in wideband power amplifier design suitable for envelope tracking (ET) is proposed. A 40 dBm decade bandwidth 0.4–4.1 GHz PA is designed, with 10–15 dB gain and 40–62% drain efficiency. Its versatility is demonstrated by digital pre-distortion (DPD) linearized measurements resulting in adjacent channel leakage ratios (ACLR) lower than −46 dBc for various downlink signals (WCDMA, LTE, WiMAX). Second, a theory for class-J microwave frequency dynamic load modulation (DLM) PAs is derived. This connects transistor technology and load network requirements to enable power-scalable and bandwidth conscious designs. A 38 dBm PA is designed at 2.08 GHz, maintaining efficiencies >45% over 8 dB of output power back-off (OPBO) dynamic range. From this pre-study a fully packaged 86-W peak power version at 2.14 GHz is designed. ACLR after DPD is −46 dBc at a drain efficiency of 34%. For DLM PAs there is a need for varactors with large effective tuning range and high breakdown voltage. For this purpose, SiC Schottky diode varactors are developed with an effective tuning range of 6:1 and supporting a 3:1 tuning ratio at 36 V of RF swing. Nonlinear characterization to enable Q-factor extraction in the presence of distortion is proposed and demonstrated by multi-harmonic active source- and load-pull, offering insights to tunable network design. Third, a method to evaluate and optimize dual-RF input PAs, while catering to higher harmonic conditions and transistor parasitics, is proposed. The method is validated by a PA design having a peak power of 44 +/- 0.9 dBm and 6 dB OPBO PAE exceeding 45% over a 1–3 GHz bandwidth. The results in this thesis contribute with a novel device and analysis of high efficiency and wideband PAs, aiding in the design of key components for future energy efficient and high capacity wireless systems

Gallium nitride-based microwave high-power heterostructure field-effect transistors

The research described in this thesis has been carried out within a joint project between the Radboud Universiteit Nijmegen (RU) and the Technische Universiteit Eindhoven (TU/e) with the title: "Performance enhancement of GaN-based microwave power amplifiers: material, device and design issues". This project has been granted by the Dutch Technology Foundation STW under project number NAF 5040. The aims of this project have been to develop the technology required to grow state-of-the-art AlGaN/GaN epilayers on sapphire and semi-insulating (s.i.) SiC substrates using metal organic chemical vapor deposition (MOCVD) and to fabricate microwave (f > 1 GHz) high-power (Pout > 10 W) heterostructure field-effect transistors (HFETs) on these epitaxial films. MOCVD growth of AlGaN/GaN epilayers and material characterization has been done within the group Applied Materials Science (AMS) of RU. Research at the Opto-Electronic Devices group (OED) of TU/e has focused on both electrical characterization of AlGaN/GaN epilayers and design, process technology development, and characterization of GaN-based HFETs and CPW passive components. Although a considerable amount of work has been done during this research with respect to processing of CPW passive components on s.i. SiC substrates, this thesis focused on active AlGaN/GaN devices only. GaN is an excellent option for high-power/high-temperature microwave applications because of its high electric breakdown field (3 MV/cm) and high electron saturation velocity (1.5 x 107 cm/s). The former is a result of the wide bandgap (3.44 eV at RT) and enables the application of high supply voltages (> 50 V), which is one of the two requirements for highpower device performance. In addition, the wide bandgap allows the material to withstand much higher operating temperatures (300oC - 500oC) than can the conventional semiconductor materials such as Si, GaAs, and InP. A big advantage of GaN over SiC is the possibility to grow heterostructures, e.g. AlGaN/GaN. The resulting two-dimensional electron gas (2DEG) at the AlGaN/GaN heterojunction serves as the conductive channel. Large drain currents (> 1 A/mm), which are the second requirement for a power device, can be achieved because of the high electron sheet densities (> 1 x 1013 cm-2) and high electron saturation velocity. These material properties clearly indicate why GaN is a very suitable candidate for next-generation microwave high-power/high-temperature applications such as high-power amplifiers (HPAs) for GSM base stations, and microwave monolithic integrated circuits (MMICs) for radar systems. In this thesis we have presented the design, technology, and measurement results of n.i.d. AlGaN/GaN:Fe HFETs grown on s.i. 4H-SiC substrates by MOCVD. These devices have submicrometer T- or FP-gates with a gate length (Lg) of 0.7 µm and total gate widths (Wg) of 0.25 mm, 0.5 mm, and 1.0 mm, respectively. The 1.0 mm devices are capable of producing a maximum microwave output power (Pout) of 11.9 W at S-band (2 GHz - 4 GHz) using class AB bias conditions of VDS = 50 V and VGS = -4.65 V. It has to be noted that excellent scaling of Pout with Wg has been demonstrated. In addition, the associated power gain (Gp) ranges between 15 dB and 20 dB, and for the power added efficiency (PAE) values from 54 % up to 70 % have been obtained. These results clearly illustrate both the successful development of the MOCVD growth process, and the successful development and integration of process modules such as ohmic and Schottky contact technology, device isolation, electron beam lithography, surface passivation, and air bridge technology, into a process flow that enables the fabrication of state-of-the-art large periphery n.i.d. AlGaN/GaN:Fe HFETs on s.i. SiC substrates, which are perfectly suitable for application in e.g. HPAs at S-band