Decoding LDPC Codes with Probabilistic Local Maximum Likelihood Bit Flipping

Communication channels are inherently noisy making error correction coding a major topic of research for modern communication systems. Error correction coding is the addition of redundancy to information transmitted over communication channels to enable detection and recovery of erroneous information. Low-density parity-check (LDPC) codes are a class of error correcting codes that have been effective in maintaining reliability of information transmitted over communication channels. Multiple algorithms have been developed to benefit from the LDPC coding scheme to improve recovery of erroneous information. This work develops a matrix construction that stores the information error probability statistics for a communication channel. This combined with the error correcting capability of LDPC codes enabled the development of the Probabilistic Local Maximum Likelihood Bit Flipping (PLMLBF) algorithm, which is the focus of this research work

High performance binary LDPC-coded OFDM systems over indoor PLC channels

Power line communication (PLC) technology is actually among the most renowned technologies for home environments due to their low-cost installation opportunities. In this study, the bit error rate (BER) performances of binary low-density parity check (LDPC) coded orthogonal frequency-division multiplexing (OFDM) systems have been considered over indoor PLC channels. Performances comparison of diverse soft and hard decision LDPC decoder schemes such as Min-Sum (MS), weighted bit flipping (WBF), gradient descent bit-flip (GDBF), noisy gradient descent bit-flip (NGDBF) and its few variants including the single-bit NGDBF (S-NGDBF), multi-bit NGDBF (M-NGDBF) and smoothed-multi-bit NGDBF (SM-NGDBF) decoders were examined in the modeled network. To evaluate the BER performance analyses three different PLC channel scenarios were generated by using new and more realistic PLC channel model proposal were also employed. All of the simulations performed in Canete’s PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the MS or SM-NGDBF decoding algorithms are employed on the receiver side

Error-Floors of the 802.3an LDPC Code for Noise Assisted Decoding

In digital communication, information is sent as bits, which is corrupted by the noise present in wired/wireless medium known as the channel. The Low Density Parity Check (LDPC) codes are a family of error correction codes used in communication systems to detect and correct erroneous data at the receiver. Data is encoded with error correction coding at the transmitter and decoded at the receiver. The Noisy Gradient Descent BitFlip (NGDBF) decoding algorithm is a new algorithm with excellent decoding performance with relatively low implementation requirements. This dissertation aims to characterize the performance of the NGDBF algorithm. A simple improvement over NGDBF called the Re-decoded NGDBF (R-NGDBF) is proposed to enhance the performance of NGDBF decoding algorithm. A general method to estimate the decoding parameters of NGDBF is presented. The estimated parameters are then verified in a hardware implementation of the decoder to validate the accuracy of the estimation technique

A Practical Nonbinary Decoder for Low-Density Parity-Check Codes with Packet-Sized Symbols

This paper presents a practical decoder for regular low-density parity-check (LDPC) codes with flexible packet-sized symbols. The proposed hMP-VSD (Combined hard-decision message-passing with vector symbol decoding) is much less complex than the conventional VSD and has the same decoding performance. Regular LDPC codes with systematic encoding are selected for implementation. The channel is assumed to be the q-ary symmetric channel (q-SC). Different code lengths and column weights of LDPC codes are investigated. The results show that the codes with a column weight of 7 provide the best performance for hMP-VSD, while hMP works best with codes having a column weight of 5. With packet-sized symbols, even the rather short (60, 30) code structure has code lengths of 1,920 to 245,760 bits with symbol sizes of 32 to 4,096 bits. Both the decoder and its encoder were implemented on Raspberry-pi 4 model B boards and these results confirm that the computation time of hMP-VSD is 60% to 70% lower than that of VSD for pe in the range 0.05 to 0.1

Low-Density Parity-Check Code Decoder Design and Error Characterization on an FPGA Based Framework

Low-Density Parity-Check (LDPC) codes have gained popularity in communication systems and standards due to their capacity approaching error correction performance. Among all the hard-decision based LDPC decoders, Gallager B (GaB), due to simplicity of its operations, poses as the most hardware friendly algorithm and an attractive solution for meeting the high-throughput demand in communication systems. However, GaB sufferers from poor error correction performance. In this work, we first propose a resource efficient GaB hardware architecture that delivers the best throughput while using fewest Field Programmable Gate Array (FPGA) resources with respect to the state of the art comparable LDPC decoding algorithms. We then introduce a Probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value determined based on experimental studies. We achieve up to four orders of magnitude better error correction performance than the GaB with a 3.4% improvement in normalized throughput performance. PGaB requires around 40% less energy than GaB as the probabilistic execution results with reducing the average iteration count by up to 62% compared to the GaB. We also show that our PGaB consistently results with an improvement in maximum operational clock rate compared to the state of the art implementations. In this dissertation, we also present a high throughput FPGA based framework to accelerate error characterization of the LDPC codes. Our flexible framework allows the end user adjust the simulation parameters and rapidly study various LDPC codes and decoders. We first show that the connection intensive bipartite graph based LDPC decoder hardware architecture creates routing stress for longer codewords that are utilized in today's communications systems and standards. We address this problem by partitioning each processing element (PE) in the bipartite graph in such a way that the inputs of a PE are evenly distributed over its partitions. This allows depopulating the Loo Up Table (LUT) resources utilized for the decoder architecture by spreading the logic across the FPGA. We show that even though LUT usage increases, critical path delay reduces with the depopulation. More importantly, with the depopulation technique an unroutable design becomes routable, which allows longer codewords to be mapped on the FPGA. We then conduct two experiments on error correction performance analysis for the GaB and PGaB algorithms, demonstrate our framework's ability to reach a resolution level that is not attainable with general purpose processor (GPP) based simulations, which reduces the time scale of simulations to 24 hours from an estimated 199 years. We finally conduct the first study on identifying all possible codewords that are not correctable by the GaB for the case where a codeword has four errors. We reduce the time scale of this simulation that requires processing 117 billion codewords to 4 hours and 38 minutes with our framework from an estimated 7800 days on a single GPP