Memristor-Based Resistive Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design

The computer memory system has both volatile and non volatile memory. The Volatile memories such as SRAM and DRAM used as a main memory and non volatile memory like flash memory. But in recent days new non volatile technologies are invented that promise the rapid changes in the landscape of memory systems. Memristor is a two terminal passive element whose resistance depends on the magnitude and polarity of the voltage applied to it. It has nonlinear relationship between voltages and current which is similar to memory devices. In this paper we approach to design memristor based nonvolatile 6-T static random access memory (SRAM) and analysis the circuit performance with conventional 6-T SRAM cell in order to prove the parameter optimizations. Then we address the memristor-based resistive random access memory (MRRAM) which is similar to that of static random access memory (SRAM) cell and we compare the nonvolatile characteristics of MRRAM with SRAM cell. Index terms: NV memory, memristor, SRAM, Resistive RAM, SPICE model

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/ semiconductor surface. The combination of these two memristive effects into multiterminal metal–oxide–semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal–oxide–semiconductor (CMOS) cofabrication with a CMOS-compatible process

Hybrid perovskite characterization and device applications.

Hybrid perovskites are a group of materials that has shown a great impact in the field of scientific research in the past decade due to the efficiency gain within a short period of time. Hot casting is one technique that has been producing high efficient and stable solar cells. Electrical transportation of lateral device structure by such film is explored to understand basic properties and predict possible device applications using it. Under dark, memristive ability of the film was explored using various experiments. Unique uni-polar memristor ability was observed. Using the experimental results, a model is hypothesized using the concepts of inbuilt potential, ion motion and carrier generation in the film. For three terminal devices unique n-type behavior in the presence of light condition and ambi-polar behavior under dark condition was observed. Reversible inert gas sensing ability of the film is explored using the surface conductivity with extra light. Getting better performances in the device applications as well as to understand overall behavior of the film it-self were discussed in the following thesis

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Content Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing

As a promising alternative to the Von Neumann architecture, in-memory computing holds the promise of delivering high computing capacity while consuming low power. Content addressable memory (CAM) can implement pattern matching and distance measurement in memory with massive parallelism, making them highly desirable for data-intensive applications. In this paper, we propose and demonstrate a novel 1-transistor-per-bit CAM based on the ferroelectric reconfigurable transistor. By exploiting the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM can be realized in a single transistor. By eliminating the need for the complementary circuit, these non-volatile CAMs based on reconfigurable transistors can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multi-bit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and stored entries. Furthermore, utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real-time without changing the layout. These reconfigurable circuits will serve as important building blocks for high-density data-stream processors and reconfigurable Application-Specific Integrated Circuits (r-ASICs). The CAMs and transformable logic gates based on ferroelectric reconfigurable transistors will have broad applications in data-intensive applications from image processing to machine learning and artificial intelligence

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Flexible Electronics for Neurological Electronic Skin with Multiple Sensing Modalities

The evolution of electronic skin (E-skin) technology in the past decade has resulted in a great variety of flexible electronic devices that mimic the physical and chemical sensing properties of skin for applications in advanced robotics, prosthetics, and health monitoring technologies. The further advancement of E-skin technology demands closer imitation of skin receptors\u27 transduction mechanisms, simultaneous detection of multiple information from different sources, and the study of transmission, processing and memory of the signals among the neurons. Motivated by such demands, this thesis focuses on design, fabrication, characterization of novel flexible electronic devices and integration of individual devices to realize prototype biomimetic E-skin with neurological and multimodal sensing functions. More specifically, we have studied flexible carbon nanotube thin-film transistors (CNT-TFTs) as control and signal processing units of E-skin and flexible ferroelectret nanogenerator (FENG) and triboelectric nanogenerator (TENG) as skin mechanoreceptors. Multiple fabrication methods, such as low-cost printing and conventional cleanroom-based microfabrication have been implemented to fabricate flexible CNT-TFTs with different structures and functions, especially the synaptic functions. Based on the research on individual devices, we have demonstrated a prototype force-sensing flexible neurological E-skin and its sensory nerve and synapse, with FENG serving as the sensory mechanoreceptor that generates action potentials (pulsed voltages) to be processed and transmitted by the flexible synaptic CNT-TFT. It allows for instantaneous detection of force stimuli and offers biological synapse-like behavior to store the stimulus information and relay the stimulus signals to the next stage. The force-sensing neurological E-skin was further augmented with visual and auditory sensing modalities by introducing phototransistor-based optical sensor and FENG-based acoustic sensor. Successful transduction of visual, auditory and tactile stimuli and synaptic processing and memory of those signals have all been demonstrated. Thanks to the multimodal sensing capability of the neurological E-skin, psychological associative learning experiment-“Pavlov’s dog\u27s experiment”, was also successfully implemented electronically by synergizing actual visual and auditory signals in the synaptic transistor. Flexible electronics and prototype neurological E-skin system demonstrated in this thesis may offer an entry into novel multimodal, user-environment interactive soft E-skin system for soft robotic and diagnostic applications

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that are distinctly different from those used for CMOS technologies. In this paper, three alternative emerging technologies are showcased in terms of their re- quirements for design implementation and in terms of poten- tial advantages. First, a CMOS evolutionary approach based on vertically-stacked gate-all-around Si nanowire FETs is discussed. Next, an alternative design methodology based on ambipolar carbon nanotube FETs is presented. Finally, a novel approach based on the recently discovered memristive devices is presented, offering the possibility of combining memory and logic functions