1,630 research outputs found

    Undergraduate Catalog of Studies, 2023-2024

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    Design and Evaluation of a Hardware System for Online Signal Processing within Mobile Brain-Computer Interfaces

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    Brain-Computer Interfaces (BCIs) sind innovative Systeme, die eine direkte Kommunikation zwischen dem Gehirn und externen Geräten ermöglichen. Diese Schnittstellen haben sich zu einer transformativen Lösung nicht nur für Menschen mit neurologischen Verletzungen entwickelt, sondern auch für ein breiteres Spektrum von Menschen, das sowohl medizinische als auch nicht-medizinische Anwendungen umfasst. In der Vergangenheit hat die Herausforderung, dass neurologische Verletzungen nach einer anfänglichen Erholungsphase statisch bleiben, die Forscher dazu veranlasst, innovative Wege zu beschreiten. Seit den 1970er Jahren stehen BCIs an vorderster Front dieser Bemühungen. Mit den Fortschritten in der Forschung haben sich die BCI-Anwendungen erweitert und zeigen ein großes Potenzial für eine Vielzahl von Anwendungen, auch für weniger stark eingeschränkte (zum Beispiel im Kontext von Hörelektronik) sowie völlig gesunde Menschen (zum Beispiel in der Unterhaltungsindustrie). Die Zukunft der BCI-Forschung hängt jedoch auch von der Verfügbarkeit zuverlässiger BCI-Hardware ab, die den Einsatz in der realen Welt gewährleistet. Das im Rahmen dieser Arbeit konzipierte und implementierte CereBridge-System stellt einen bedeutenden Fortschritt in der Brain-Computer-Interface-Technologie dar, da es die gesamte Hardware zur Erfassung und Verarbeitung von EEG-Signalen in ein mobiles System integriert. Die Architektur der Verarbeitungshardware basiert auf einem FPGA mit einem ARM Cortex-M3 innerhalb eines heterogenen ICs, was Flexibilität und Effizienz bei der EEG-Signalverarbeitung gewährleistet. Der modulare Aufbau des Systems, bestehend aus drei einzelnen Boards, gewährleistet die Anpassbarkeit an unterschiedliche Anforderungen. Das komplette System wird an der Kopfhaut befestigt, kann autonom arbeiten, benötigt keine externe Interaktion und wiegt einschließlich der 16-Kanal-EEG-Sensoren nur ca. 56 g. Der Fokus liegt auf voller Mobilität. Das vorgeschlagene anpassbare Datenflusskonzept erleichtert die Untersuchung und nahtlose Integration von Algorithmen und erhöht die Flexibilität des Systems. Dies wird auch durch die Möglichkeit unterstrichen, verschiedene Algorithmen auf EEG-Daten anzuwenden, um unterschiedliche Anwendungsziele zu erreichen. High-Level Synthesis (HLS) wurde verwendet, um die Algorithmen auf das FPGA zu portieren, was den Algorithmenentwicklungsprozess beschleunigt und eine schnelle Implementierung von Algorithmusvarianten ermöglicht. Evaluierungen haben gezeigt, dass das CereBridge-System in der Lage ist, die gesamte Signalverarbeitungskette zu integrieren, die für verschiedene BCI-Anwendungen erforderlich ist. Darüber hinaus kann es mit einer Batterie von mehr als 31 Stunden Dauerbetrieb betrieben werden, was es zu einer praktikablen Lösung für mobile Langzeit-EEG-Aufzeichnungen und reale BCI-Studien macht. Im Vergleich zu bestehenden Forschungsplattformen bietet das CereBridge-System eine bisher unerreichte Leistungsfähigkeit und Ausstattung für ein mobiles BCI. Es erfüllt nicht nur die relevanten Anforderungen an ein mobiles BCI-System, sondern ebnet auch den Weg für eine schnelle Übertragung von Algorithmen aus dem Labor in reale Anwendungen. Im Wesentlichen liefert diese Arbeit einen umfassenden Entwurf für die Entwicklung und Implementierung eines hochmodernen mobilen EEG-basierten BCI-Systems und setzt damit einen neuen Standard für BCI-Hardware, die in der Praxis eingesetzt werden kann.Brain-Computer Interfaces (BCIs) are innovative systems that enable direct communication between the brain and external devices. These interfaces have emerged as a transformative solution not only for individuals with neurological injuries, but also for a broader range of individuals, encompassing both medical and non-medical applications. Historically, the challenge of neurological injury being static after an initial recovery phase has driven researchers to explore innovative avenues. Since the 1970s, BCIs have been at one forefront of these efforts. As research has progressed, BCI applications have expanded, showing potential in a wide range of applications, including those for less severely disabled (e.g. in the context of hearing aids) and completely healthy individuals (e.g. entertainment industry). However, the future of BCI research also depends on the availability of reliable BCI hardware to ensure real-world application. The CereBridge system designed and implemented in this work represents a significant leap forward in brain-computer interface technology by integrating all EEG signal acquisition and processing hardware into a mobile system. The processing hardware architecture is centered around an FPGA with an ARM Cortex-M3 within a heterogeneous IC, ensuring flexibility and efficiency in EEG signal processing. The modular design of the system, consisting of three individual boards, ensures adaptability to different requirements. With a focus on full mobility, the complete system is mounted on the scalp, can operate autonomously, requires no external interaction, and weighs approximately 56g, including 16 channel EEG sensors. The proposed customizable dataflow concept facilitates the exploration and seamless integration of algorithms, increasing the flexibility of the system. This is further underscored by the ability to apply different algorithms to recorded EEG data to meet different application goals. High-Level Synthesis (HLS) was used to port algorithms to the FPGA, accelerating the algorithm development process and facilitating rapid implementation of algorithm variants. Evaluations have shown that the CereBridge system is capable of integrating the complete signal processing chain required for various BCI applications. Furthermore, it can operate continuously for more than 31 hours with a 1800mAh battery, making it a viable solution for long-term mobile EEG recording and real-world BCI studies. Compared to existing research platforms, the CereBridge system offers unprecedented performance and features for a mobile BCI. It not only meets the relevant requirements for a mobile BCI system, but also paves the way for the rapid transition of algorithms from the laboratory to real-world applications. In essence, this work provides a comprehensive blueprint for the development and implementation of a state-of-the-art mobile EEG-based BCI system, setting a new benchmark in BCI hardware for real-world applicability

    Undergraduate Catalog of Studies, 2023-2024

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    A 39-GHz Doherty-Like Power Amplifier with 22-dBm Output Power and 21% Power-Added Efficiency at 6-dB Power Back-Off

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    © 2024, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/JETCAS.2024.3351075The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical loadmodulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non-50 Ω load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the SLMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power (Psat) with a maximum poweradded efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVMrms) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadratureamplitude- modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.Peer reviewe

    Neuromorphic hardware for somatosensory neuroprostheses

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    In individuals with sensory-motor impairments, missing limb functions can be restored using neuroprosthetic devices that directly interface with the nervous system. However, restoring the natural tactile experience through electrical neural stimulation requires complex encoding strategies. Indeed, they are presently limited in effectively conveying or restoring tactile sensations by bandwidth constraints. Neuromorphic technology, which mimics the natural behavior of neurons and synapses, holds promise for replicating the encoding of natural touch, potentially informing neurostimulation design. In this perspective, we propose that incorporating neuromorphic technologies into neuroprostheses could be an effective approach for developing more natural human-machine interfaces, potentially leading to advancements in device performance, acceptability, and embeddability. We also highlight ongoing challenges and the required actions to facilitate the future integration of these advanced technologies

    Optical ground receivers for satellite based quantum communications

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    Cryptography has always been a key technology in security, privacy and defence. From ancient Roman times, where messages were sent cyphered with simple encoding techniques, to modern times and the complex security protocols of the Internet. During the last decades, security of information has been assumed, since classical computers do not have the power to break the passwords used every day (if they are generated properly). However, in 1984, a new threat emerged when Peter Shor presented the Shor’s algorithm, an algorithm that could be used in quantum computers to break many of the secure communication protocols nowadays. Current quantum computers are still in their early stages, with not enough qubits to perform this algorithm in reasonable times. However, the threat is present, not future, since the messages that are being sent by important institutions can be stored, and decoded in the future once quantum computers are available. Quantum key distribution (QKD) is one of the solutions proposed for this threat, and the only one mathematically proven to be secure with no assumptions on the eavesdropper power. This optical technology has recently gained interest to be performed with satellite communications, the main reason being the relative ease to deploy a global network in this way. In satellite QKD, the parameter space and available technology to optimise are very big, so there is still a lot of work to be done to understand which is the optimal way to exploit this technology. This dissertation investigates one of these parameters, the encoding scheme. Most satellite QKD systems use polarisation schemes nowadays. This thesis presents for the first time an experimental work of a time-bin encoding scheme for free-space receivers within a full QKD system in the second chapter. The third and fourth chapter explore the advantages of having multi-protocol free-space receivers that can boost the interoperability between systems, polarisation filtering techniques to reduce background. Finally, the last chapter presents a new technology that can help increase communications rates

    Undergraduate Catalog of Studies, 2022-2023

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    RF Wireless Power and Data Transfer : Experiment-driven Analysis and Waveform Design

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    The brisk deployment of the fifth generation (5G) mobile technology across the globe has accelerated the adoption of Internet of Things (IoT) networks. While 5G provides the necessary bandwidth and latency to connect the trillions of IoT sensors to the internet, the challenge of powering such a multitude of sensors with a replenishable energy source remains. Far-field radio frequency (RF) wireless power transfer (WPT) is a promising technology to address this issue. Conventionally, the RF WPT concepts have been deemed inadequate to deliver wireless power due to the undeniably huge over-the-air propagation losses. Nonetheless, the radical decline in the energy requirement of simple sensing and computing devices over the last few decades has rekindled the interest in RF WPT as a feasible solution for wireless power delivery to IoT sensors. The primary goal in any RF WPT system is to maximize the harvested direct current (DC) power from the minuscule incident RF power. As a result, optimizing the receiver power efficiency is pivotal for an RF WPT system. On similar lines, it is essential to minimize the power losses at the transmitter in order to achieve a sustainable and economically viable RF WPT system. In this regard, this thesis explores the system-level study of an RF WPT system using a digital radio transmitter for applications where alternative analog transmit circuits are impractical. A prototype test-bed comprising low-cost software-defined radio (SDR) transmitter and an off-the-shelf RF energy-harvesting (EH) receiver is developed to experimentally analyze the impact of clipping and nonlinear amplification at the digital radio transmitter on digital baseband waveform. The use of an SDR allows leveraging the test-bed for the research on RF simultaneous wireless information and power transfer (SWIPT); the true potential of this technology can be realized by utilizing the RF spectrum to transport data and power together. The experimental results indicate that a digital radio severely distorts high peak-to-average power ratio (PAPR) signals, thereby reducing their average output power and rendering them futile for RF WPT. On similar lines, another test-bed is developed to assess the impact of different waveforms, input impedance mismatch, incident RF power, and load on the receiver power efficiency of an RF WPT system. The experimental results provide the foundation and notion to develop a novel mathematical model for an RF EH receiver. The parametric model relates the harvested DC power to the power distribution of the envelope signal of the incident waveform, which is characterized by the amplitude, phase and frequency of the baseband waveform. The novel receiver model is independent of the receiver circuit’s matching network, rectifier configuration, number of diodes, load as well as input frequency. The efficacy of the model in accurately predicting the output DC power for any given power-level distribution is verified experimentally. Since the novel receiver model associates the output DC power to the parameters of the incident waveform, it is further leveraged to design optimal transmit wave-forms for RF WPT and SWIPT. The optimization problem reveals that a constant envelope signal with varying duty cycle is optimal for maximizing the harvested DC power. Consequently, a pulsed RF waveform is optimal for RF WPT, whereas a continuous phase modulated pulsed RF signal is suitable for RF SWIPT. The superior WPT performance of pulsed RF waveforms over multisine signals is demonstrated experimentally. Similarly, the pulsed phase-shift keying (PSK) signals exhibit superior receiver power efficiency than other communication signals. Nonetheless, varying the duty-cycle of pulsed PSK waveform leads to an efficiency—throughput trade-off in RF SWIPT. Finally, the SDR test-bed is used to evaluate the overall end-to-end power efficiency of different digital baseband waveforms through wireless measurements. The results indicate a 4-PSK modulated signal to be suitable for RF WPT considering the overall power efficiency of the system. The corresponding transmitter, channel and receiver power efficiencies are evaluated as well. The results demonstrate the transmitter power efficiency to be lower than the receiver power efficiency

    Nonvolatile CMOS memristor, reconfigurable array and its application in power load forecasting

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    © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/TII.2023.3341256The high cost, low yield, and low stability of nano-materials significantly hinder the application and development of memristors. To promote the application of memristors, researchers proposed a variety of memristor emulators to simulate memristor functions and apply them in various fields. However these emulators lack nonvolatile characteristics, limiting their scope of application. This paper proposes an innovative nonvolatile memristor circuit based on complementary metal-oxide-semiconductor (CMOS) technology, expanding the horizons of memristor emulators. The proposed memristor is fabricated in a reconfigurable array architecture using the standard CMOS process, allowing the connection between memristors to be altered by configuring the on-off state of switches. Compared to nano-material memristors, the CMOS nonvolatile memristor circuit proposed in this paper offers advantages of low manufacturing cost and easy mass production, which can promote the application of memristors. The application of the reconfigurable array is further studied by constructing an Echo State Network (ESN) for short-term load forecasting in the power system.Peer reviewe

    Beam scanning by liquid-crystal biasing in a modified SIW structure

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    A fixed-frequency beam-scanning 1D antenna based on Liquid Crystals (LCs) is designed for application in 2D scanning with lateral alignment. The 2D array environment imposes full decoupling of adjacent 1D antennas, which often conflicts with the LC requirement of DC biasing: the proposed design accommodates both. The LC medium is placed inside a Substrate Integrated Waveguide (SIW) modified to work as a Groove Gap Waveguide, with radiating slots etched on the upper broad wall, that radiates as a Leaky-Wave Antenna (LWA). This allows effective application of the DC bias voltage needed for tuning the LCs. At the same time, the RF field remains laterally confined, enabling the possibility to lay several antennas in parallel and achieve 2D beam scanning. The design is validated by simulation employing the actual properties of a commercial LC medium
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