A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V

Automated Mixed Traffic Vehicle (AMTV) technology and safety study

Technology and safety related to the implementation of an Automated Mixed Traffic Vehicle (AMTV) system are discussed. System concepts and technology status were reviewed and areas where further development is needed are identified. Failure and hazard modes were also analyzed and methods for prevention were suggested. The results presented are intended as a guide for further efforts in AMTV system design and technology development for both near term and long term applications. The AMTV systems discussed include a low speed system, and a hybrid system consisting of low speed sections and high speed sections operating in a semi-guideway. The safety analysis identified hazards that may arise in a properly functioning AMTV system, as well as hardware failure modes. Safety related failure modes were emphasized. A risk assessment was performed in order to create a priority order and significant hazards and failure modes were summarized. Corrective measures were proposed for each hazard

A CMOS implementation of a spike event coding scheme for analog arrays

This paper presents a CMOS circuit implementation of a spike event coding/decoding scheme for transmission of analog signals in a programmable analog array. This scheme uses spikes for a time representation of analog signals. No spikes are transmitted using this scheme when signals are constant, leading to low power dissipation and traffic reduction in a shared channel. A proof-of-concept chip was designed in a 0.35 mum process and experimental results are presented

Reconfigurable nanoelectronics using graphene based spintronic logic gates

This paper presents a novel design concept for spintronic nanoelectronics that emphasizes a seamless integration of spin-based memory and logic circuits. The building blocks are magneto-logic gates based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and present a spin-based circuit design with smaller area, faster speed, and lower energy consumption than the state-of-the-art CMOS counterparts. This design can also be applied in applications such as data compression, coding and image recognition. In the proposed scheme, over 100 spin-based logic operations are carried out before any need for a spin-charge conversion. Consequently, supporting CMOS electronics requires little power consumption. The spintronic-CMOS integrated system can be implemented on a single 3-D chip. These nonvolatile logic circuits hold potential for a paradigm shift in computing applications.Comment: 14 pages (single column), 6 figure

Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.Comment: 15 pages, contribution to the 2014 CAS - CERN Accelerator School: Power Converters, Baden, Switzerland, 7-14 May 201

Static and dynamic nonlinearity compensation techniques for high performance current-steering digital-to-analog converters

High-speed high-accuracy digital-to-analog converters (DACs) are the crucial building blocks for many signal processing and telecommunication systems. The current-steering architecture is extensively used for these applications. With different decoding schemes--binary-weighted, unary-coded, and segment-coded, current-steering DACs are realized by groups of matched current sources. Their performance is limited by many nonlinear mechanisms such as random mismatch errors, gradient effect, code and voltage dependence of finite output impedance, nonlinear settling time, charge injection, and switch timing errors. In this thesis, two nonlinearity compensation techniques are presented to improve the overall performance of the current-steering DACs. The first design technique is a novel digital calibration technique--complete-folding, which effectively compensates the random mismatch errors by selectively regrouping current sources into a fully binary-weighted array based on current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes complete-folding calibration suitable for DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to the DAC without using any calibration. Additional results also show that this new calibration technique has the superior performance in compensating random mismatch errors as compared to state-of-the-art. The second design technique is a novel output impedance linearization technique that very effectively reduces the code and voltage dependence of finite output impedance. The linearization is achieved by using a small DAC switched with control signals opposite to those for the main DAC. The area and power overhead is less than 5% of the main DAC. Simulation results with a 14-bit segmented current-steering DAC in standard 0.18μm CMOS process show that the DAC\u27s integral nonlinearity (INL) due to finite output impedance is improved by almost 5 bits. Additional results show that this technique is very robust to random mismatch errors. Moreover, not only the static linearity is improved, but most importantly there is a large dynamic linearity enhancement by output impedance linearization. Simulation results show that spurious-free dynamic range (SFDR) can be improved by almost 30 dB at the low signal frequencies and more than 8 dB for the high signal frequencies up to Nyquist rate while sampling at 500MS/s

A Digital-to-Analog Converter Architecture for Multi-Channel Applications

Systems-on-chip with the capability of driving multiple analog voltages are useful for a variety of applications, including multiple actuator control for robotics applications, automated test equipment systems, industrial automation, programmable logic controllers, and satellite ywheel motor control. Such applications require a DAC for each analog output. A multi-channel architecture that saves power and area by sharing hardware is needed. This work introduces a new single-ramp multi-channel 12-bit DAC architecture. The architecture includes a low power Gray code counter, ramp generator, digital comparator, analog memory units, and control logic. The new multi-channel DAC architecture allows hardware sharing between multiple channels, and enables Systems-on-Chip to have multiple analog outputs for stimulating transducers or motors. The DAC architecture is to be used in a variety of space and defense applications as part of the BAE Systems RAD6000 microcontroller project