This paper presents a CMOS circuit implementation of a spike event coding/decoding scheme for transmission of analog signals in a programmable analog array. This scheme uses spikes for a time representation of analog signals. No spikes are transmitted using this scheme when signals are constant, leading to low power dissipation and traffic reduction in a shared channel. A proof-of-concept chip was designed in a 0.35 mum process and experimental results are presented

Gouveia, L.C.

Hamilton, A.

Koickal, T.J.

English

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A CMOS implementation of a spike event coding scheme for analog arrays

Enlighten: Publications

  
 
 
 
 
 
 Gouveia, L.C., Koickal, T.J., and Hamilton, A. (2009) A CMOS 
implementation of a spike event coding scheme for analog arrays. In: 2009 
IEEE International Symposium on Circuits and Systems, 24-27 May 2009, 
Taipei, China. 
 
 
Copyright © 2009 IEEE 
 
 
A copy can be downloaded for personal non-commercial research or 
study, without prior permission or charge  
 
The content must not be changed in any way or reproduced in any format 
or medium without the formal permission of the copyright holder(s)  
 
When referring to this work, full bibliographic details must be given 
 
 
 
 
 
http://eprints.gla.ac.uk/76501/ 
 
 
 
 
 
 
Deposited on:  8 March 2013 
 
 
 
 
 
 
 
 
 
Enlighten – Research publications by members of the University of Glasgow 
http://eprints.gla.ac.uk 
A CMOS Implementation of a Spike Event Coding
Scheme for Analog Arrays
Luiz Carlos Gouveia, Thomas Jacob Koickal and Alister Hamilton
Institute for Micro and Nano Systems - School of Engineering and Joint Research Institute for Integrated Systems
University of Edinburgh, EH9 3JL, U.K.
Email: L.Gouveia@ed.ac.uk, {Thomas.Koickal, Alister.Hamilton}@ee.ed.ac.uk
Abstract— This paper presents a CMOS circuit implementa-
tion of a spike event coding/decoding scheme for transmission of
analog signals in a programmable analog array. This scheme uses
spikes for a time representation of analog signals. No spikes are
transmitted using this scheme when signals are constant, leading
to low power dissipation and traffic reduction in a shared channel.
A proof-of-concept chip was designed in a 0.35µm process and
experimental results are presented.
I. INTRODUCTION
Configurable Analog Blocks (CABs) are the basic pro-
cessing units of Field Programmable Analog Arrays (FPAAs)
and are configured to perform different types of analog func-
tions [1]. The communication between CABs is an important
issue because traditional techniques like crossbars or switch
matrices [2] degrade the transmitted signals. These techniques
cause distortion of the signal due to voltage drops, parasitic
capacitances along wires and the switches and through signal
interference, limiting the size of analog arrays.
Pulse modulations are an alternative to these techniques.
They map the amplitude of analog signals onto the timing
domain. The use of these discrete-amplitude continuous-time
modulations allows greater system scalability than analog
routing methods. Synchronous versions were used in analog
arrays [3], but as they require a global clock signal, these mod-
ulations suffer from clock skew and high power consumption.
Asynchronous modulations are used in some biological
inspired systems [5] [6]. Recently, a spike event coding
scheme was proposed by the authors to transmit analog signals
between CABs [4]. It presents advantages over other pulse
modulations, such as transmission of information on demand
and, therefore, reduction in communication traffic, and low
energy dissipation, freedom from clock skew and low crosstalk
due to asynchronous coding.
In this paper we present a CMOS implementation of the
spike event coding scheme with programmable resolution.
First we review the working principles of the scheme. Later,
we describe the design parameters and the circuits used to
realize the coder. Finally, we present results from a tested
chip.
II. SPIKE EVENT CODING SCHEME
The spike event coding scheme [4] is shown in Fig. 1(a).
The spike event coder operates by generating a signal similar
to the input signal. In other words, a feedback signal z(t) is
   
channel
   
x(t) e(t) y(t)
z(t)
z
R
(t)y
R
(t) x
R
(t)
Spike 
Generator
V
th1
c
1
(t)Coder Decoder
INTC
INTD LPF
k
I
k
I
V
th2
c
2
(t)
∫
∫
(a)
x(t)
z(t)
y(t) t
∆z(t)
t = t
1
1 2 N
p
...
t = t
0 1 Nn
...
δ
T ∆t
D
x(t)
(b)
Fig. 1. (a) Block diagram of the spike event coding scheme and (b) an
example of the behavior of the main signals. δ is the tracking step, T is the
spike width and ∆tD is the time interval between successive spikes.
forced to track the input signal x(t) by bounding the error e(t)
between them:
e(t) = x(t)− z(t) = x(t)−
∫
y(t)dt (1)
where y(t) is the coder output. This output is represented
either by positive or negative pulses with a short and fixed
duration (spikes). These spikes are produced by the spike
generator and transmitted both to the communication channel
and to the input of the feedback integrator (INTC).
Each positive or negative spike results in an incremental
or decremental change δ (tracking step) at the output of the
feedback integrator:
∆z(t) = δ (Np−Nn) (2)
where Np (Nn) is the number of previous positive (negative)
spikes since t0 as shown in Fig. 1(b).
Considering an ideal channel, the spikes are also transmitted
to the decoder integrator INTD, which presents the same
gain KI of the coder feedback integrator INTC. The decoder
output xR(t) is given by:
xR(t) ≈
∫
y(t)dt = z(t) = x(t)− e(t) (3)
with the decoder Low Pass Filter (LPF) removing high fre-
quency harmonics and averaging the signal zR(t). Therefore,
the maximum difference between the decoder output xR(t)
and coder input x(t) is |e(t)|max, which is defined by the
specification of the spike event scheme resolution:
|e(t)|max =
∆x(t)max
2NB − 1
(4)
where ∆x(t)max is the input dynamic range and NB is the
desired resolution in bits.
III. ANALOG VLSI IMPLEMENTATION
The spike event coding scheme was implemented in a
proof-of-concept chip for validation of the scheme. The layout
dimensions of the spike event coder are 240µm x 120µm using
AMS 0.35µm CMOS process.
In this section we describe the spike event coder and decoder
circuits implemented on chip: comparators, spike generator
and integrators. Both coder and decoder integrators were
implemented using the same design. The decoder LPF was
implemented off-chip, using an offline digital filter.
A. Comparators
In the block diagram in Fig. 1(a), the error e(t) is limited
by two comparators with different thresholds (Vth1 and Vth2):
|e| ≤ ∆Vth = |Vth1 − Vth2| (5)
From (4) and (5), the resolution of the spike event coding
scheme is a function of the thresholds of both comparators.
The design of the comparators can be implemented using
a preamplifier (PA) followed by a decision circuit (DC) and
an output buffer (OB) [7]. To provide the required ∆Vth,
capacitive or resistive dividers can be used at the comparator
input nodes. However, these dividers compromise the input
impedance of the circuit.
Another method to provide ∆Vth is to implement offset
comparators. Composite transistors can be used to provide the
offset [8], however this topology suffers from low dynamic
range. A programmable offset can also be generated by
another preamplifier which provide a respective ∆Ioff on the
decision circuit input [9]. Both impedance dividers and offset
comparators allow continuous resolution values to be used.
In this implementation, both outputs c1(t) and c2(t) are
generated by a compound comparator in Fig. 2. Instead of
using four preamplifiers, with two sensing the inputs x(t)
and z(t) and two providing different offsets, we use only
two preamplifiers. The preamplifier PAA outputs a differential
current ∆Ixz as the result of the comparison between x(t) and
z(t). Thus, the capacitive loads of these nodes are reduced
by using only one preamplifier. The other preamplifier (PAB)
provides a differential current ∆Ioff/2 according to ∆Vth/2
x(t)
PAA
+
_
A
B
OB2∆Vth/2
c
2
(t)
z(t)
OB1
c
1
(t)
PAB
+
_
A
B
DC1
C
D
DC2
C
D
∆I
xz
∆I
off
/2
Fig. 2. Block diagram of the compound comparator. Preamplilfier PAA
outputs a current ∆Ixz according to the inputs x(t) and z(t), while
preamplifier PAB generate a fixed offset current ∆Ioff/2. PAB outputs are
added or subtracted from PAA outputs and the results are applied to the
respective decision circuits (DC) and output buffers (OB).
M2
Ibias
M4
M1
M3
+ −
Vss
Vdd
B
1,2
A
1,2
PA
M5,7M6,8
M12 M11
Vdd
M13
M10 M9
M15
M17
M14
M16
C D
Vss
Vdd
M18
M19
Vout
DC
OB
Fig. 3. Circuit schematic of each of the compound comparator blocks.
Transconductance preamplifier (PA,left), decision circuit (DC,top right) and
output stage (OB,bottom right).
voltage on the inputs. The results of adding ( ∆Ixz+∆Ioff/2)
and subtracting (∆Ixz−∆Ioff/2) these currents are forwarded
to the decision circuits to speed up the comparison result.
Finally, output buffers generate the digital outputs.
Fig. 3 presents the preamplifier, the decision and the
output buffer schematic circuits implemented on chip. The
preamplifier is a transconductance amplifier with two identical
differential output currents at nodes (A1, B1) and (A2, B2).
The decision circuit is a positive feedback circuit and the
output buffer is a self-biased amplifier [10].
B. Spike Generator
The spike generator block can provide either a positive or a
negative spike according to the output state of the comparator.
When the error e > ∆Vth/2, a negative spike is transmitted.
Similarly, a positive spike is generated when e < −∆Vth/2.
Otherwise, no spikes are transmitted. The control circuitry
for this logic was implemented using a technique for the
design of asynchronous digital circuits [11]. These spikes can
be transmitted using switch matrices or any asynchronous
Medium Access Channel (MAC) protocol, like AER [12].
M24
1.5 I
M26
M20
M22
Vdd
d
2
Vss
1.5 I
d
1
M23
0.5 I
M21
M27
M25
Vdd
d
4
Vss
0.5 I
d
3
C
int
z(t), z
R
(t)
dpdp inc dec
dpdp incdec
Fig. 4. Schematic of the integrator based on a charge pump technique.
When a positive spike arrives, M20 and M21 turn on and 1.5I and 0.5I
charges and discharges the capacitor Cint, respectively, resulting in a voltage
increment of δd = T × I/Cint. For negative spikes, the complementary
process decreases the capacitor voltage. In the absence of spikes, currents are
drawn to low impedance nodes (d1-d4). The schematic of the delay generators
is not shown.
C. Integrators
In this implementation, the spike width T is used in the
integrator block to increment or decrement z(t) by δ. A
minimum interspike interval ∆tDmin = kT is also introduced
in the design to avoid overload on the communication channel
(“refractory period”). The coder output spike frequency is a
function of the magnitude of the input derivative and the coder
integration step:
f =
∣∣∣dx(t)dt
∣∣∣
δ
=
1
T +∆tD
(6)
The first conclusion from (6) is that no spikes are transmitted
when the input derivative is zero, i.e. the input signal is
constant. This is true only after the feedback signal z(t) has
tracked the input signal x(t), i.e. e(t) ≤ ∆Vth.
We also conclude from (6) that the maximum output fre-
quency occurs when the input signal presents its maximum
absolute input derivative. From the specification of this deriva-
tive, ∆tDmin is defined and pulse width T is:
T =
δ
(k + 1)
∣∣∣dx(t)dt
∣∣∣
max
(7)
The integrator block includes programmable delay circuits
for the generation of T and ∆tDmin time intervals.
For an optimum performance, the tracking step δ is equal
to the difference between the thresholds ∆Vth of the com-
parators. Setting δ < ∆Vth, more output spikes will be
needed for the feedback signal z(t) track the input signal x(t).
Conversely, z(t) will oscillate for δ > ∆Vth. However, a
design margin is required because of the random offsets
present in the comparator due to process variations. Therefore,
the designed tracking step is:
δd ≤ ∆Vth − 6σ(Vos) (8)
where σ(Vos) is the comparator offset standard deviation.
We implemented the integrator block using a charge pump
integrator as shown in Fig. 4. A unipolar version of this type
of circuit driving resistors is used in steering current cells of
some Digital-to-Analog Converters (DACs).
When a negative spike arrives at the integrator input, the dec
signal turns high during an interval T , allowing currents 1.5I
and 0.5I flowing in transistors M22 and M23, respectively.
Similarly, for the case of a positive spike arrival, transistors
M20 and M21 provide symmetrical operation with inc and
inc signals. The resulting current I that discharges or charges
the integrating capacitor Cint is given by I = Cint × δd/T .
Therefore, the integration gain is given by KI = δd/T . When
there are no spikes, currents are driven to low impedance nodes
(d1-d4) through M24-M27 by setting the signal dp high.
The use of two different branches (M22 and M23 or M20
and M21) to both charge and discharge the capacitor reduces
charge injection on the integration node [13] at the cost of
doubling the power consumption required. If switches M20
and M21 (M22 and M23) have the same dimensions, the
charges injected from the gate to drain capacitance of the
complimentary switches cancel each other.
IV. CHIP RESULTS
We used two different input signals to test the chip: a speech
signal and a sine wave. The speech signal was sampled at 44.1
kSps with 8 bit resolution. The coder was designed to provide
a resolution of 6 bits. The coder input signal x(t), the decoder
integrator output zR(t) and the coder output spikes y(t) are
shown in Fig. 5(a). The same signals are presented in detail in
Fig. 5(b) to show the absence of coder output spikes when the
signal is constant or when its change is smaller than ∆Vth.
The resolution of the system was measured using a sine
wave input signal. The sine wave presents 1.0 Vpp amplitude
and 4.4 kHz frequency (fin) sampled at 555 kSps and the
coder was designed to provide a 4 bit resolution. A snapshot
of the input and output signals is presented in Fig. 6(a). Offline
filtering results are shown in the Fig. 6(b) for a digital LPF
with a cutoff frequency of 4.4 kHz, the same frequency as the
input signal.
The measured resolution of the pre-filter signal is 3.83 bits.
The resolution increases to 6.97 and 5.29 bits for post-
filter signals, using filter cut-off frequencies equals to fin
and 10fin, respectively. However, this resolution improvement
causes attenuation and phase shift of the signal. These results
are similar to the simulation values presented in [4]. The
measured power consumption of the coder is 0.4 mW, with
approximately 90% of if used by the comparator.
V. CONCLUSIONS
In this paper we described a CMOS implementation of a
spike event coding scheme. This scheme is intended to be
used to transmit analog signals inside a FPAA and/or between
different FPAAs using asynchronous events (spikes).
This scheme presents an efficient utilization of channel re-
sources and lower power consumption because no output activ-
ity is present when signals are constant. A chip was designed
(a)
(b)
Fig. 5. (a) Coder input x(t) and decoder integrator output zR(t) for a
2.5Vpp speech signal. Negative (ON) and positive (OP) output coder spikes
are also shown at the bottom of the figure. (b) A detailed view of the same
waveforms to show the absence of spikes during the periods when the input
signal is constant.
in a 0.35µm process and the experimental results validate the
circuit design. This scheme is being implemented within a
small array of CABs developed by the authors [14] [15].
ACKNOWLEDGMENT
The authors would like to thank the supports from En-
gineering and Physical Sciences Research Council and the
Scottish Funding Council for the Joint Research Institute with
the Heriot-Watt University, part of the Edinburgh Research
Partnership in Engineering and Mathematics (ERPem).
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[4] Gouveia, L., Koickal, T. and Hamilton, A., ”An asynchronous spike event
coding scheme for programmable analog arrays”, in Proceedings of the
IEEE International Symposium on Circuits and Systems, 2008, pp.1364-
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(a)
0.0159 0.0159 0.016 0.016 0.0161
−0.5
0
0.5
Time (s)
Am
pl
itu
de
0 1 2 3 4 5 6 7
x 104
−50
0
Frequency (Hz)
dB
 
 
ZR(s)
XR(t)
x(t)
zR(t)
xR(t)
(b)
Fig. 6. (a) Snapshot of 1.0Vpp sine wave input x(t) and decoder integrator
output zR(t) and negative (ON) and positive (OP) spikes from coder output
(bottom). (b) x(t), zR(t) and the low pass filter output xR(t) (top). The low
pass filter cut-off frequency is the same as the input signal. The frequency
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Enlighten

        Gouveia, L.C., Koickal, T.J., and Hamilton, A. (2009) A CMOS implementation of a spike event coding scheme for analog arrays. In: 2009 IEEE International Symposium on Circuits and Systems, 24-27 May 2009, Taipei, China.   Copyright © 2009 IEEE   A copy can be downloaded for personal non-commercial research or study, without prior permission or charge   The content must not be changed in any way or reproduced in any format or medium without the formal permission of the copyright holder(s)   When referring to this work, full bibliographic details must be given      http://eprints.gla.ac.uk/76501/       Deposited on:  8 March 2013          Enlighten – Research publications by members of the University of Glasgow http://eprints.gla.ac.uk A CMOS Implementation of a Spike Event CodingScheme for Analog ArraysLuiz Carlos Gouveia, Thomas Jacob Koickal and Alister HamiltonInstitute for Micro and Nano Systems - School of Engineering and Joint Research Institute for Integrated SystemsUniversity of Edinburgh, EH9 3JL, U.K.Email: L.Gouveia@ed.ac.uk, {Thomas.Koickal, Alister.Hamilton}@ee.ed.ac.ukAbstract— This paper presents a CMOS circuit implementa-tion of a spike event coding/decoding scheme for transmission ofanalog signals in a programmable analog array. This scheme usesspikes for a time representation of analog signals. No spikes aretransmitted using this scheme when signals are constant, leadingto low power dissipation and traffic reduction in a shared channel.A proof-of-concept chip was designed in a 0.35µm process andexperimental results are presented.I. INTRODUCTIONConfigurable Analog Blocks (CABs) are the basic pro-cessing units of Field Programmable Analog Arrays (FPAAs)and are configured to perform different types of analog func-tions [1]. The communication between CABs is an importantissue because traditional techniques like crossbars or switchmatrices [2] degrade the transmitted signals. These techniquescause distortion of the signal due to voltage drops, parasiticcapacitances along wires and the switches and through signalinterference, limiting the size of analog arrays.Pulse modulations are an alternative to these techniques.They map the amplitude of analog signals onto the timingdomain. The use of these discrete-amplitude continuous-timemodulations allows greater system scalability than analogrouting methods. Synchronous versions were used in analogarrays [3], but as they require a global clock signal, these mod-ulations suffer from clock skew and high power consumption.Asynchronous modulations are used in some biologicalinspired systems [5] [6]. Recently, a spike event codingscheme was proposed by the authors to transmit analog signalsbetween CABs [4]. It presents advantages over other pulsemodulations, such as transmission of information on demandand, therefore, reduction in communication traffic, and lowenergy dissipation, freedom from clock skew and low crosstalkdue to asynchronous coding.In this paper we present a CMOS implementation of thespike event coding scheme with programmable resolution.First we review the working principles of the scheme. Later,we describe the design parameters and the circuits used torealize the coder. Finally, we present results from a testedchip.II. SPIKE EVENT CODING SCHEMEThe spike event coding scheme [4] is shown in Fig. 1(a).The spike event coder operates by generating a signal similarto the input signal. In other words, a feedback signal z(t) is   channel   x(t) e(t) y(t)z(t)zR(t)yR(t) xR(t)Spike GeneratorVth1c1(t)Coder DecoderINTCINTD LPFkIkIVth2c2(t)∫∫(a)x(t)z(t)y(t) t∆z(t)t = t11 2 Np...t = t0 1 Nn...δT ∆tDx(t)(b)Fig. 1. (a) Block diagram of the spike event coding scheme and (b) anexample of the behavior of the main signals. δ is the tracking step, T is thespike width and ∆tD is the time interval between successive spikes.forced to track the input signal x(t) by bounding the error e(t)between them:e(t) = x(t)− z(t) = x(t)−∫y(t)dt (1)where y(t) is the coder output. This output is representedeither by positive or negative pulses with a short and fixedduration (spikes). These spikes are produced by the spikegenerator and transmitted both to the communication channeland to the input of the feedback integrator (INTC).Each positive or negative spike results in an incrementalor decremental change δ (tracking step) at the output of thefeedback integrator:∆z(t) = δ (Np−Nn) (2)where Np (Nn) is the number of previous positive (negative)spikes since t0 as shown in Fig. 1(b).Considering an ideal channel, the spikes are also transmittedto the decoder integrator INTD, which presents the samegain KI of the coder feedback integrator INTC. The decoderoutput xR(t) is given by:xR(t) ≈∫y(t)dt = z(t) = x(t)− e(t) (3)with the decoder Low Pass Filter (LPF) removing high fre-quency harmonics and averaging the signal zR(t). Therefore,the maximum difference between the decoder output xR(t)and coder input x(t) is |e(t)|max, which is defined by thespecification of the spike event scheme resolution:|e(t)|max =∆x(t)max2NB − 1(4)where ∆x(t)max is the input dynamic range and NB is thedesired resolution in bits.III. ANALOG VLSI IMPLEMENTATIONThe spike event coding scheme was implemented in aproof-of-concept chip for validation of the scheme. The layoutdimensions of the spike event coder are 240µm x 120µm usingAMS 0.35µm CMOS process.In this section we describe the spike event coder and decodercircuits implemented on chip: comparators, spike generatorand integrators. Both coder and decoder integrators wereimplemented using the same design. The decoder LPF wasimplemented off-chip, using an offline digital filter.A. ComparatorsIn the block diagram in Fig. 1(a), the error e(t) is limitedby two comparators with different thresholds (Vth1 and Vth2):|e| ≤ ∆Vth = |Vth1 − Vth2| (5)From (4) and (5), the resolution of the spike event codingscheme is a function of the thresholds of both comparators.The design of the comparators can be implemented usinga preamplifier (PA) followed by a decision circuit (DC) andan output buffer (OB) [7]. To provide the required ∆Vth,capacitive or resistive dividers can be used at the comparatorinput nodes. However, these dividers compromise the inputimpedance of the circuit.Another method to provide ∆Vth is to implement offsetcomparators. Composite transistors can be used to provide theoffset [8], however this topology suffers from low dynamicrange. A programmable offset can also be generated byanother preamplifier which provide a respective ∆Ioff on thedecision circuit input [9]. Both impedance dividers and offsetcomparators allow continuous resolution values to be used.In this implementation, both outputs c1(t) and c2(t) aregenerated by a compound comparator in Fig. 2. Instead ofusing four preamplifiers, with two sensing the inputs x(t)and z(t) and two providing different offsets, we use onlytwo preamplifiers. The preamplifier PAA outputs a differentialcurrent ∆Ixz as the result of the comparison between x(t) andz(t). Thus, the capacitive loads of these nodes are reducedby using only one preamplifier. The other preamplifier (PAB)provides a differential current ∆Ioff/2 according to ∆Vth/2x(t)PAA+_ABOB2∆Vth/2c2(t)z(t)OB1c1(t)PAB+_ABDC1CDDC2CD∆Ixz∆Ioff/2Fig. 2. Block diagram of the compound comparator. Preamplilfier PAAoutputs a current ∆Ixz according to the inputs x(t) and z(t), whilepreamplifier PAB generate a fixed offset current ∆Ioff/2. PAB outputs areadded or subtracted from PAA outputs and the results are applied to therespective decision circuits (DC) and output buffers (OB).M2IbiasM4M1M3+ −VssVddB1,2A1,2PAM5,7M6,8M12 M11VddM13M10 M9M15M17M14M16C DVssVddM18M19VoutDCOBFig. 3. Circuit schematic of each of the compound comparator blocks.Transconductance preamplifier (PA,left), decision circuit (DC,top right) andoutput stage (OB,bottom right).voltage on the inputs. The results of adding ( ∆Ixz+∆Ioff/2)and subtracting (∆Ixz−∆Ioff/2) these currents are forwardedto the decision circuits to speed up the comparison result.Finally, output buffers generate the digital outputs.Fig. 3 presents the preamplifier, the decision and theoutput buffer schematic circuits implemented on chip. Thepreamplifier is a transconductance amplifier with two identicaldifferential output currents at nodes (A1, B1) and (A2, B2).The decision circuit is a positive feedback circuit and theoutput buffer is a self-biased amplifier [10].B. Spike GeneratorThe spike generator block can provide either a positive or anegative spike according to the output state of the comparator.When the error e > ∆Vth/2, a negative spike is transmitted.Similarly, a positive spike is generated when e < −∆Vth/2.Otherwise, no spikes are transmitted. The control circuitryfor this logic was implemented using a technique for thedesign of asynchronous digital circuits [11]. These spikes canbe transmitted using switch matrices or any asynchronousMedium Access Channel (MAC) protocol, like AER [12].M241.5 IM26M20M22Vddd2Vss1.5 Id1M230.5 IM21M27M25Vddd4Vss0.5 Id3Cintz(t), zR(t)dpdp inc decdpdp incdecFig. 4. Schematic of the integrator based on a charge pump technique.When a positive spike arrives, M20 and M21 turn on and 1.5I and 0.5Icharges and discharges the capacitor Cint, respectively, resulting in a voltageincrement of δd = T × I/Cint. For negative spikes, the complementaryprocess decreases the capacitor voltage. In the absence of spikes, currents aredrawn to low impedance nodes (d1-d4). The schematic of the delay generatorsis not shown.C. IntegratorsIn this implementation, the spike width T is used in theintegrator block to increment or decrement z(t) by δ. Aminimum interspike interval ∆tDmin = kT is also introducedin the design to avoid overload on the communication channel(“refractory period”). The coder output spike frequency is afunction of the magnitude of the input derivative and the coderintegration step:f =∣∣∣dx(t)dt∣∣∣δ=1T +∆tD(6)The first conclusion from (6) is that no spikes are transmittedwhen the input derivative is zero, i.e. the input signal isconstant. This is true only after the feedback signal z(t) hastracked the input signal x(t), i.e. e(t) ≤ ∆Vth.We also conclude from (6) that the maximum output fre-quency occurs when the input signal presents its maximumabsolute input derivative. From the specification of this deriva-tive, ∆tDmin is defined and pulse width T is:T =δ(k + 1)∣∣∣dx(t)dt∣∣∣max(7)The integrator block includes programmable delay circuitsfor the generation of T and ∆tDmin time intervals.For an optimum performance, the tracking step δ is equalto the difference between the thresholds ∆Vth of the com-parators. Setting δ < ∆Vth, more output spikes will beneeded for the feedback signal z(t) track the input signal x(t).Conversely, z(t) will oscillate for δ > ∆Vth. However, adesign margin is required because of the random offsetspresent in the comparator due to process variations. Therefore,the designed tracking step is:δd ≤ ∆Vth − 6σ(Vos) (8)where σ(Vos) is the comparator offset standard deviation.We implemented the integrator block using a charge pumpintegrator as shown in Fig. 4. A unipolar version of this typeof circuit driving resistors is used in steering current cells ofsome Digital-to-Analog Converters (DACs).When a negative spike arrives at the integrator input, the decsignal turns high during an interval T , allowing currents 1.5Iand 0.5I flowing in transistors M22 and M23, respectively.Similarly, for the case of a positive spike arrival, transistorsM20 and M21 provide symmetrical operation with inc andinc signals. The resulting current I that discharges or chargesthe integrating capacitor Cint is given by I = Cint × δd/T .Therefore, the integration gain is given by KI = δd/T . Whenthere are no spikes, currents are driven to low impedance nodes(d1-d4) through M24-M27 by setting the signal dp high.The use of two different branches (M22 and M23 or M20and M21) to both charge and discharge the capacitor reducescharge injection on the integration node [13] at the cost ofdoubling the power consumption required. If switches M20and M21 (M22 and M23) have the same dimensions, thecharges injected from the gate to drain capacitance of thecomplimentary switches cancel each other.IV. CHIP RESULTSWe used two different input signals to test the chip: a speechsignal and a sine wave. The speech signal was sampled at 44.1kSps with 8 bit resolution. The coder was designed to providea resolution of 6 bits. The coder input signal x(t), the decoderintegrator output zR(t) and the coder output spikes y(t) areshown in Fig. 5(a). The same signals are presented in detail inFig. 5(b) to show the absence of coder output spikes when thesignal is constant or when its change is smaller than ∆Vth.The resolution of the system was measured using a sinewave input signal. The sine wave presents 1.0 Vpp amplitudeand 4.4 kHz frequency (fin) sampled at 555 kSps and thecoder was designed to provide a 4 bit resolution. A snapshotof the input and output signals is presented in Fig. 6(a). Offlinefiltering results are shown in the Fig. 6(b) for a digital LPFwith a cutoff frequency of 4.4 kHz, the same frequency as theinput signal.The measured resolution of the pre-filter signal is 3.83 bits.The resolution increases to 6.97 and 5.29 bits for post-filter signals, using filter cut-off frequencies equals to finand 10fin, respectively. However, this resolution improvementcauses attenuation and phase shift of the signal. These resultsare similar to the simulation values presented in [4]. Themeasured power consumption of the coder is 0.4 mW, withapproximately 90% of if used by the comparator.V. CONCLUSIONSIn this paper we described a CMOS implementation of aspike event coding scheme. This scheme is intended to beused to transmit analog signals inside a FPAA and/or betweendifferent FPAAs using asynchronous events (spikes).This scheme presents an efficient utilization of channel re-sources and lower power consumption because no output activ-ity is present when signals are constant. A chip was designed(a)(b)Fig. 5. (a) Coder input x(t) and decoder integrator output zR(t) for a2.5Vpp speech signal. Negative (ON) and positive (OP) output coder spikesare also shown at the bottom of the figure. (b) A detailed view of the samewaveforms to show the absence of spikes during the periods when the inputsignal is constant.in a 0.35µm process and the experimental results validate thecircuit design. This scheme is being implemented within asmall array of CABs developed by the authors [14] [15].ACKNOWLEDGMENTThe authors would like to thank the supports from En-gineering and Physical Sciences Research Council and theScottish Funding Council for the Joint Research Institute withthe Heriot-Watt University, part of the Edinburgh ResearchPartnership in Engineering and Mathematics (ERPem).REFERENCES[1] Lee, E.K. and Gulak, P.G., ”A CMOS field-programmable analog array”.IEEE Journal of Solid-State Circuits, vol. 26, no. 12, pp. 1860-1867,December 1991.[2] D’Mello, D. R. and Gulak, P. G., ”Design approaches to field-programmable analog integrated circuits”. Special Issue on Pro-grammable Analog Systems, Analog Integrated Circuits and Signal Pro-cessing, Hingham: Kluwer Academic Publishers, vol. 17, no. 1-2, pp.7-34, September 1998.[3] Papathanasiou, K., Brandtner, T. and Hamilton, A., ”Palmo: pulse-basedsignal processing for programmable analog VLSI”. IEEE Transactionson Circuits and Systems-II, Analog and Digital Signal Processing, vol.49, no. 6, pp. 379-389, June 2002.[4] Gouveia, L., Koickal, T. and Hamilton, A., ”An asynchronous spike eventcoding scheme for programmable analog arrays”, in Proceedings of theIEEE International Symposium on Circuits and Systems, 2008, pp.1364-1367.(a)0.0159 0.0159 0.016 0.016 0.0161−0.500.5Time (s)Amplitude0 1 2 3 4 5 6 7x 104−500Frequency (Hz)dB  ZR(s)XR(t)x(t)zR(t)xR(t)(b)Fig. 6. (a) Snapshot of 1.0Vpp sine wave input x(t) and decoder integratoroutput zR(t) and negative (ON) and positive (OP) spikes from coder output(bottom). (b) x(t), zR(t) and the low pass filter output xR(t) (top). The lowpass filter cut-off frequency is the same as the input signal. The frequencyspectrum ZR(s) and XR(s) of the filter input and output (bottom).[5] Lazar, A.A. and Toth, L.T., ”Perfect recovery and sensitivity analysisof time encoded bandlimited signals”, IEEE Transactions on Circuitsand Systems I: Fundamental Theory and Applications, vol.51, no.10, pp.2060-2073, October 2004.[6] Wei, D. and Harris, J.G., ”Signal reconstruction from spiking neuronmodels”. Proceedings of the International Symposium on Circuits andSystems, vol. 5, pp. 353-356, May 2004.[7] Baker, R.J., Li, H.W. and Boyce, D.E., CMOS: Circuit Design, Layoutand Simulation. New York:IEEE Press, 1998.[8] Fayed, A.A. and Ismail, M., ”A High Speed, Low Voltage CMOS OffsetComparator”, Analog Integrated Circuits and Signal Processing, vol. 36,no. 3, pp. 267-272, September 2003.[9] Yaklin, D., ”Offset Comparator with Common Mode Voltage Stability”,U. S. Patent 5517134, May 1997.[10] Bazes, M., ”Two novel fully complementary self-biased CMOS differ-ential amplifiers”, IEEE Journal of Soild-State Circuits, vol. 26, pp. 165-168, February 1991.[11] Martin, A., ”Translating Concurrent Programs into VLSI Chips”, inProceedings of the 4th International PARLE Conference on ParallelArchitectures and Languages EuropeI, London:Springer-Verlag, 1992, pp.515-532.[12] Boahen, K., ”Point-to-point connectivity between neuromorphic chipsusing address events”, IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing, vol. 47, no. 5, pp. 416-434, May2000.[13] Pan, H., ”Method and system for a glitch-free differential currentsteering switch circuit for high speed, high resolution digital-to-analogconversion”, US Patent US20060092062, May 2006.[14] Koickal, T., Hamilton, A. and Gouveia, L., ”Programmable analog VLSIarchitecture based upon event coding”, Second NASA/ESA Conference onAdaptive Hardware and Systems, pp. 554-562, August 2007.[15] Koickal, T., Hamilton, A. and Gouveia, L., ”Bio-inspired Event CodedConfigurable Analog Circuit Block”, Evolvable Systems: From Biologyto Hardware, LNCS 5216, Berlin:Springer-Verlag, 2008, pp. 285-295.

A CMOS ﬁeld-programmable analog array”.

An asynchronous spike event coding scheme for programmable analog arrays”,

Palmo: pulse-based signal processing for programmable analog VLSI”.

http://eprints.gla.ac.uk/76501/1/76501.pdf

A CMOS implementation of a spike event coding scheme for analog arrays

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