Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Perturbation of the sierpinski antenna to allocate the operating bands

A scheme for modifying the spacing between the bands of the Sierpinski antenna is introduced. Experimental results of two novel designs of fractal antennas suggest that the fractal structure can be perturbed to enable the log-period to be changed while still maintaining the multiband behaviour of the antenna.Peer ReviewedPostprint (published version

Generation and optimization of picosecond optical pulses for use in hybrid WDM/OTDM networks

The burgeoning demand for broadband services such as database queries, home shopping, video-on-demand, remote education, telemedicine and videoconferencing will push the existing networks to their limits. This demand was mainly fueled by the brisk proliferation of Personal Computers (PC) together with the exceptional increases in their storage capacity and processing capabilities and the widespread availability of the internet. Hence the necessity, to develop high-speed optical technologies in order to construct large capacity networks, arises. Two of the most popular multiplexing techniques available in the optical domain that are used in the building of such high capacity networks, are Wavelength Division Multiplexing (WDM) and Optical Time Division Multiplexing (OTDM). However merging these two techniques to form very high-speed hybrid WDM/OTDM networks brings about the merits of both multiplexing technologies. This thesis examines the development of one of the key components (picosecond optical pulses) associated to such high-speed systems. Recent analysis has shown that RZ format is superior to conventional NRZ systems as it is easier to compensate for dispersion and nonlinear effects in the fibre by employing soliton-like propagation. In addition to this development, the use of wavelength tunability for dynamic provisioning is another area that is actively researched on. Self-seeding of a gain switched Fabry Perot laser is shown to one of the simplest and cost effective methods of generating, transform limited optical pulses that are wavelength tunable over very wide ranges. One of the vital characteristics of the above mentioned pulse sources, is their Side Mode Suppression Ratio (SMSR). This thesis examines in detail how the pulse SMSR affects the performance of high-speed WDM/OTDM systems that employ self-seeded gain-switched pulse sources

A Low-Power Interface for Capacitive Sensors With PWM Output and Intrinsic Low Pass Characteristic

A compact, low power interface for capacitive sensors, is described. The output signal is a pulse width modulated (PWM) signal, where the pulse duration is linearly proportional to the sensor differential capacitance. The original conversion approach consists in stimulating the sensor capacitor with a triangular-like voltage waveform in order to obtain a square-like current waveform, which is subsequently demodulated and integrated over a clock period. The charge obtained in this way is then converted into the output pulse duration by an approach that includes an intrinsic tunable low pass function. The main non idealities are thoroughly investigated in order to provide useful design indications and evaluate the actual potentialities of the proposed circuit. The theoretical predictions are compared with experimental results obtained with a prototype, designed and fabricated using 0.32 mu M CMOS devices from the BCD6s process of STMicroelectroncs. The prototype occupies a total area of 1025 x 515 mm(2) and is marked by a power consuption of 84 mu W. The input capacitance range is 0-256 fF, with a resolution of 0.8 fF and a temperature sensitivity of 300 ppm/degrees C

LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos

Radio-frequency integrated-circuit design for CMOS single-chip UWB systems

Low cost, a high-integrated capability, and low-power consumption are the basic requirements for ultra wide band (UWB) system design in order for the system to be adopted in various commercial electronic devices in the near future. Thus, the highly integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF blocks in CMOS for UWB for commercial applications. In this dissertation, there is a discussion of the development, as well as an illustration, of a fully-integrated ultra-broadband transmit/receive (T/R) switch which uses nMOS transistors with deep n-well in a standard 0.18-μm CMOS process. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET’s parasitic capacitances in order to synthesize artificial transmission lines which result in low insertion loss over an extremely wide bandwidth. Within DC-10 GHz, 10-18 GHz, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0 and 2.5 dB and isolation between 32-60 dB, 25-32 dB, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. Further, there is a discussion and demonstration of a tunable Carrier-based Time-gated UWB transmitter in this dissertation which uses a broadband multiplier, a novel fully integrated single pole single throw (SPST) switch designed by the CMOS process, where a tunable instantaneous bandwidth from 500 MHz to 4 GHz is exhibited by adjusting the width of the base band impulses in time domain. The SPST switch utilizes the synthetic transmission line concept and multiple reflections technique in order to realize a flat insertion loss less than 1.5 dB from 3.1 GHz to 10.6 GHz and an extremely high isolation of more than 45 dB within this frequency range. A fully integrated complementary LC voltage control oscillator (VCO), designed with a tunable buffer, operates from 4.6 GHz to 5.9 GHz. The measurement results demonstrate that the integrated VCO has a very low phase noise of –117 dBc/ Hz at 1 MHz offset. The fully integrated VCO achieves a very high figure of merit (FOM) of 183.5 using standard CMOS process while consuming 4 mA DC current

Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction

The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity. A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level. The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency

Eighth International Workshop on Laser Ranging Instrumentation

The Eighth International Workshop for Laser Ranging Instrumentation was held in Annapolis, Maryland in May 1992, and was sponsored by the NASA Goddard Space Flight Center in Greenbelt, Maryland. The workshop is held once every 2 to 3 years under differing institutional sponsorship and provides a forum for participants to exchange information on the latest developments in satellite and lunar laser ranging hardware, software, science applications, and data analysis techniques. The satellite laser ranging (SLR) technique provides sub-centimeter precision range measurements to artificial satellites and the Moon. The data has application to a wide range of Earth and lunar science issues including precise orbit determination, terrestrial reference frames, geodesy, geodynamics, oceanography, time transfer, lunar dynamics, gravity and relativity

A 3.2 GHz Injection-Locked Ring Oscillator-Based Phase-Locked-Loop for Clock Recovery

An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type oscillators. These excellent performances come at the expense of a very poor integration density. To alleviate this issue, this work introduces an injection-locked ring oscillator-based PLL circuit. The combination of the injection-locking process with the use of ring oscillators allows for the benefit of excellent jitter performance while presenting an extremely low surface area due to an architecture without any inductor. The injection locking principle is addressed, and evidence of its phase noise and jitter improvements are confirmed through measurement results. Indeed, phase noise and jitter enhancements up to 43 dB and 23.3 mUI, respectively, were measured. As intended, this work shows the best integration density compared to recent similar state-of-the-art studies. The whole architecture measures 0.1 mm2 while consuming 34.6 mW in a low-cost 180 nm CMOS technology

Elements of a 200 watt pulsed excimer laser

This thesis describes the theoretical and experimental investigation into many aspects of circuit and component design for high average power short pulse systems. The primary objective of this work is to develop both circuit design criteria and pulsed components for long life rare gas halide lasers. A pulsed system consists of three major components, energy storage, switches, and load. This investigation considers the type of circuit which uses capacitive energy storage in combination with a closing switch to transfer electrical power to a load. Specific loads are not addressed but the implications of load characteristics that affect circuit/component design and life are considered. The investigation reported, describes the physical and electrical characteristics and analysis of phenomena that adversely affect the performance and life of pulse duty components. In the area of capacitive storage, lifetimes of one particular design was improved by 3 orders of magnitude and a means of detecting the imminent failure of oil filled capacitors was devised and patented. In the area of switching, methods are described by which hydrogen thyratrons can be operated in parallel with equal current sharing without the need for inductive or resistive ballasting. Finally, the design and testing of a 200 watt XeCl laser modulator is presented