High Current Matching over Full-Swing and Low-Glitch Charge Pump Circuit for PLLs

A high current matching over full-swing and low-glitch charge pump (CP) circuit is proposed. The current of the CP is split into two identical branches having one-half the original current. The two branches are connected in source-coupled structure, and a two-stage amplifier is used to regulate the common-source voltage for the minimum current mismatch. The proposed CP is designed in TSMC 0.18µm CMOS technology with a power supply of 1.8 V. SpectreRF based simulation results show the mismatch between the current source and the current sink is less than 0.1% while the current is 40 µA and output swing is 1.32 V ranging from 0.2 V to 1.52 V. Moreover, the transient output current presents nearly no glitches. The simulation results verify the usage of the CP in PLLs with the maximum tuning range from the voltage-controlled oscillator, as well as the low power supply applications

Switched-capacitor step-down rectifier for low-voltage power conversion

This paper presents a switched-capacitor rectifier that provides step down voltage conversion from an ac input voltage to a dc output. Coupled with current-drive source, low-loss and high step-down rectification is realized. Implementation in CMOS with appropriate controls results in a design suitable for low-voltage very-high-frequency conversion. Applications include switched-capacitor rectification to convert high-frequency ac to a dc output and, combined with inversion and transformation, to dc-dc converters for low-voltage outputs. A two-step CMOS integrated full-bridge switched-capacitor rectifier is implemented in TSMC 0.25 μm CMOS technology for demonstration purposes. For an operation frequency of 50 MHz and an output voltage of 2.5 V, the peak efficiency of the rectifier is 81% at a power level of 4 W.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation

Techniques for low power analog, digital and mixed signal CMOS integrated circuit design

With the continuously expanding of market for portable devices such as wireless communication devices, portable computers, consumer electronics and implantable medical devices, low power is becoming increasingly important in integrated circuits. The low power design can increase operation time and/or utilize a smaller size and lighter-weight battery. In this dissertation, several low power complementary metal-oxide-semiconductor (CMOS) integrated circuit design techniques are investigated. A metal-oxide-semiconductor field effect transistor (MOSFET) can be operated at a lower voltage by forward-biasing the source-substrate junction. This approach has been investigated in detail and used to designing an ultra-low power CMOS operational amplifier for operation at ± 0.4 V. The issue of CMOS latchup and noise has been investigated in detail because of the forward biasing of the substrates of MOSFETs in CMOS. With increasing forward body-bias, the leakage current increases significantly. Dynamic threshold MOSFET (DTMOS) technique is proposed to overcome the drawback which is inherent in a forward-biased MOSFET. By using the DTMOS method with the forward source-body biased MOSFET, two low-power low-voltage CMOS VLSI circuits that of a CMOS analog multiplexer and a Schmitt trigger circuits are designed. In this dissertation, an adaptive body-bias technique is proposed. Adaptive body-bias voltage is generated for several operational frequencies. Another issue, which the chip design community is facing, is the development of portable, cost effective and low power supply voltage. This dissertation proposes a new cost-effective DC/DC converter design in standard 1.5 um n-well CMOS, which adopts a delay-line controller for voltage regulation

CMOS/Bipolar current conveyor design and development

The aim of this research programme was to design and develop a novel CMOS current conveyor, to improve areas such as bandwidth, slew rate, gain, and Powe- Supply Reject Ratio (PSRR). The current conveyor can be used in low frequency applications such as LED drivers for mobile phones and televisions, and high frequency applications such as mixers for up/down converters used in anything from radios to mobile phones. The initial part of the research looked into improving the Power Supply Rejection Ration (PSRR) of the current follower (mirror) by increasing its output impedance. Several types of current mirror were compared using analytical and simulation methods, using a new generic low frequency transistor model which was used to highlight the differences in impedance between BJT and CMOS current mirrors. It was found that the best type of mirror was the regulated cascode current mirror which offered the largest value of output impedance when built from CMOS transistors. Work then moved onto the voltage follower. By initially using a typical CMOS source follower, it was found that the voltage gain suffered from low values transconductance, drain/source resistance, and a larger than expected value of source resistance, which was extracted from simulation and was found to be around 300- 350Q. The best design was a two stage un-buffered amplifier which offered the best Power Supply Rejection (PSRR) voltage gain and bandwidth. Several different types of current conveyor (CCII+) were simulated and the results were compared. It was found that the best types of current conveyor were the cascode type conveyors which offered a voltage gain error of less than 1%. The regulated cascode type current conveyor offered the highest figure of PSRR that of around 60dB. Finally the new cascode type current conveyors were used to build examples of current feedback operational amplifiers (CFOAs), and the cascode type CCIl+ offered a voltage gain error of less than I%, largest bandwidth and best P SRR

Low Voltage and High Performance Constant Current Source using 90nm CMOStechnology

This paper proposed a self-biasing constantcurrent source circuit which is suitable for analog integrated and mixed mode circuits.A low input resistance, high output resistance and high gain current source is proposed. This current source circuit is designed by using five n-type and two p-type MOSFETs. Simulation is performed with 90nm digital CMOS technology.Accuracy and gainare the most important parameters to observe the performance of the Current Source. This current source is operated at 0.8V supply voltage

Class-AB rail-to-rail CMOS buffer with bulk-driven super source followers

This paper describes a rail-to-rail CMOS analog voltage buffer designed to have extremely low static current consumption as well as high current drive capability. The buffer employs a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilized to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation. The proposed buffer has been designed for a 0.35 mum CMOS technology to operate at a 1.8 V supply voltage. The simulated results are provided to demonstrate that the total harmonic distortion for a 1.6 Vpp 100 kHz sine wave with a 68 pF load is as low as -46 dB, whilst the static current consumption remains under 8 muA

Low Power High Gain Op-Amp using Square Root based Current Generator

A very high gain two stage CMOS operational amplifier has been presented The proposed circuit is implemented in 180nm CMOS technology with a supply voltage of 0 65V The current source in the OPAMP is replaced by a square root based current generator which helps to reduce the impact of process variations on the circuit and low power consumption due to the operation of MOS in subthreshold region So with the help of square root based current generator the better controllability over gain can be obtained The proposed opamp shows a high gain of 121 9dB and low power consumption of 11 89uW is achieve

Thermionic charge transport in CMOS nano-transistors

We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature

Overview of ionizing radiation effects in image sensors fabricated in a deep-submicrometer CMOS imaging technology

An overview of ionizing radiation effects in imagers manufactured in a 0.18-μm CMOS image sensor technology is presented. Fourteen types of image sensors are characterized and irradiated by a 60Co source up to 5 kGy. The differences between these 14 designs allow us to separately estimate the effect of ionizing radiation on microlenses, on low- and zero-threshold-voltage MOSFETs and on several pixel layouts using P+ guard-rings and edgeless transistors. After irradiation, wavelength dependent responsivity drops are observed. All the sensors exhibit a large dark current increase attributed to the shallow trench isolation that surrounds the photodiodes. Saturation voltage rises and readout chain gain variations are also reported. Finally, the radiation hardening perspectives resulting from this paper are discussed