Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization

This paper presents an extensive, non-exhaustive, study of available hard disk drive read channel equalization techniques used in the storage and readback of magnetically stored information. The physical elements and basic principles of the storage processes are introduced together with the basic theoretical definitions and models. Both read and write processes in magnetic storage are explained along with the definition of simple key concepts such as user bit density, intersymbol interference, linear and areal density, read head pulse response models, and coding algorithm

Design of adaptive analog filters for magnetic front-end read channels

Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem para canais de leitura em sistemas de gravação e reprodução de dados em suporte magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a 1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços muito significativos a nível mundial com o objectivo de se investigarem novas técnicas de realização de filtros em circuito integrado monolítico, especialmente em tecnologia CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização de soluções com as características desejadas. Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão de sinal bem como a escolha de bons modelos matemáticos para o tratamento da informação e a minimização de erro inerente às aproximações na conformidade aos princípios físicos dos dispositivos caracterizados. O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo, baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization) com base na igualização de sinal utilizando filtros integrados analógicos em tempo contínuo. Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo, dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa e análise de estruturas ideais no projecto de filtros recorrendo a representações no espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de circuitos de transcondutância para a implementação de filtros integrados analógicos em tempo contínuo. Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros no espaço de estados, correspondentes a duas soluções alternativas para a realização de um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem, para utilização num canal de leitura de dados em suporte magnético. Como parte constituinte destes filtros, apresenta-se uma técnica de realização de circuitos de transcondutância, e de realização de condensadores lineares usando matrizes de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se métodos de adaptação automática capazes de compensar os erros face aos valores nominais dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os quais apresentamos os resultados de simulação e de medição experimental obtidos. Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível de constituir uma solução para o controlo de posicionamento da cabeça de leitura em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo de igualação do canal de leitura. Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency filters. The motivation of this work was the search for filtering solutions for the readchannel in recording and reproduction of data on magnetic media systems, with costs and consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than the available circuits. Accordingly, as was done in this work, the rapid development of microelectronics technology raised very significant efforts worldwide in order to investigate new techniques for implementing such filters in monolithic integrated circuit, especially in CMOS technology (Complementary Metal Oxide Semiconductor). We present a comparative study on different hierarchical levels of the project, which led to the realization and characterization of solutions with the desired characteristics. In the first level, this study addresses the conceptual question of recording and transmission of signal and the choice of good mathematical models for the processing of information and minimization of error inherent in the approaches and in accordance with the principles of the characterized physical devices. The main work of this thesis is focused on the hierarchical levels of the architecture of the read channel and the integrated circuit implementation of its main block - the filtering block. At the architecture level of the read channel this work presents a comprehensive study on existing methodologies of adaptation and signal recovery of data on magnetic media. This project appears in the sequence of the proposed solution for a lowcost, low consumption, low voltage, low complexity, using CMOS digital technology for the performance of a DFE (Decision Feedback Equalization) based on the equalization of the signal using integrated analog filters in continuous time. At the project level of implementation of the filtering block and techniques for implementing filters and its building components, it was concluded that the technique based on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate for the implementation of very-high-frequency adaptive filters. We defined in this lower level, two sub-levels of depth study for this thesis, namely: research and analysis of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation of continuous time integrated analog filters. Following this study, we present and compare two filtering structures operating in the space of states, corresponding to two alternatives for achieving a realization of an adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a read-channel for magnetic media devices. As a constituent part of these filters, we present a technique for the realization of transconductance circuits and for the implementation of linear capacitors using arrays of MOSFET transistors for signal processing in very-high-frequency integrated circuits using sub-micrometric CMOS technology. We present methods capable of automatic adjustment and compensation for deviation errors in respect to the nominal values of the components inherent to the tolerances of the fabrication process, for which we present the simulation and experimental measurement results obtained. Also as a result of this study, is the presentation of a circuit that provides a solution for the control of the head positioning on recording/playback systems of data on magnetic media. The proposed block is an adaptive first-order filter, based on the same transconductance circuits and equalization techniques proposed and used in the implementation of the adaptive filter for the equalization of the read channel. This filter was designed and included in an integrated circuit (Jaguar) used to control the positioning of the read-head done for ATMEL company in Colorado Springs, and part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company

ON REDUCING THE DECODING COMPLEXITY OF SHINGLED MAGNETIC RECORDING SYSTEM

Shingled Magnetic Recording (SMR) has been recognised as one of the alternative technologies to achieve an areal density beyond the limit of the perpendicular recording technique, 1 Tb/in2, which has an advantage of extending the use of the conventional method media and read/write head. This work presents SMR system subject to both Inter Symbol Interference (ISI) and Inter Track Interference (ITI) and investigates different equalisation/detection techniques in order to reduce the complexity of this system. To investigate the ITI in shingled systems, one-track one-head system model has been extended into two-track one-head system model to have two interfering tracks. Consequently, six novel decoding techniques have been applied to the new system in order to find the Maximum Likelihood (ML) sequence. The decoding complexity of the six techniques has been investigated and then measured. The results show that the complexity is reduced by more than three times with 0.5 dB loss in performance. To measure this complexity practically, perpendicular recording system has been implemented in hardware. Hardware architectures are designed for that system with successful Quartus II fitter which are: Perpendicular Magnetic Recording (PMR) channel, digital filter equaliser with and without Additive White Gaussian Noise (AWGN) and ideal channel architectures. Two different hardware designs are implemented for Viterbi Algorithm (VA), however, Quartus II fitter for both of them was unsuccessful. It is found that, Simulink/Digital Signal Processing (DSP) Builder based designs are not efficient for complex algorithms and the eligible solution for such designs is writing Hardware Description Language (HDL) codes for those algorithms.The Iraqi Governmen

Integrated Transversal Equalizers in High-Speed Fiber-Optic Systems

Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-µm SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-µm multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10^-5 to less than 10^-12

EQUALISATION TECHNIQUES FOR MULTI-LEVEL DIGITAL MAGNETIC RECORDING

A large amount of research has been put into areas of signal processing, medium design, head and servo-mechanism design and coding for conventional longitudinal as well as perpendicular magnetic recording. This work presents some further investigation in the signal processing and coding aspects of longitudinal and perpendicular digital magnetic recording. The work presented in this thesis is based upon numerical analysis using various simulation methods. The environment used for implementation of simulation models is C/C + + programming. Important results based upon bit error rate calculations have been documented in this thesis. This work presents the new designed Asymmetric Decoder (AD) which is modified to take into account the jitter noise and shows that it has better performance than classical BCJR decoders with the use of Error Correction Codes (ECC). In this work, a new method of designing Generalised Partial Response (GPR) target and its equaliser has been discussed and implemented which is based on maximising the ratio of the minimum squared euclidean distance of the PR target to the noise penalty introduced by the Partial Response (PR) filter. The results show that the new designed GPR targets have consistently better performance in comparison to various GPR targets previously published. Two methods of equalisation including the industry's standard PR, and a novel Soft-Feedback- Equalisation (SFE) have been discussed which are complimentary to each other. The work on SFE, which is a novelty of this work, was derived from the problem of Inter Symbol Interference (ISI) and noise colouration in PR equalisation. This work also shows that multi-level SFE with MAP/BCJR feedback based magnetic recording with ECC has similar performance when compared to high density binary PR based magnetic recording with ECC, thus documenting the benefits of multi-level magnetic recording. It has been shown that 4-level PR based magnetic recording with ECC at half the density of binary PR based magnetic recording has similar performance and higher packing density by a factor of 2. A novel technique of combining SFE and PR equalisation to achieve best ISI cancellation in a iterative fashion has been discussed. A consistent gain of 0.5 dB and more is achieved when this technique is investigated with application of Maximum Transition Run (MTR) codes. As the length of the PR target in PR equalisation increases, the gain achieved using this novel technique consistently increases and reaches up to 1.2 dB in case of EEPR4 target for a bit error rate of 10-5

A 125 MHz analog adaptive equalizer for UTP5 cable

Due to the abundance and low-cost of unshielded twisted pair (UTP5) cables, there is a great deal of interest in transmitting high-speed data over long UTP5 cables. However, there are certain challenges that face circuit and system designers in accomplishing this task. The non-idealities of the cable and the data transmission system tend to limit the performance of the communication system. The frequency dependent attenuation of the cable leads to Inter Symbol Interference (ISI), which makes data recovery more difficult for larger signaling rates and larger cable lengths. A channel equalizer at the receiver end can be used to partially compensate for the frequency dependent attenuation of the cable. In this thesis a general scheme for equalization is proposed. The industry\u27s first 2V channel equalizer for UTP5 cable systems is proposed. This device has been fabricated in a 0.21u CMOS process and tested experimentally. The device has very low power dissipation (\u3c12milliwatt) and requires minimal silicon area (0.14mm*0.14mm). The target application of this equalizer is the 1394 UTP5 standard. With the proposed equalizer in a UTP5 cable equalization structure, the peak-to-peak jitter of the equalized signal obtained experimentally is less than 0.3UI (which includes 1394 driver jitter) for data rates of 125Mbps and lengths of up to 100m. Although the overall approach was to design this system for UTP5 cable equalization the concepts apply to other systems as well

CHANNEL CODING TECHNIQUES FOR A MULTIPLE TRACK DIGITAL MAGNETIC RECORDING SYSTEM

In magnetic recording greater area) bit packing densities are achieved through increasing track density by reducing space between and width of the recording tracks, and/or reducing the wavelength of the recorded information. This leads to the requirement of higher precision tape transport mechanisms and dedicated coding circuitry. A TMS320 10 digital signal processor is applied to a standard low-cost, low precision, multiple-track, compact cassette tape recording system. Advanced signal processing and coding techniques are employed to maximise recording density and to compensate for the mechanical deficiencies of this system. Parallel software encoding/decoding algorithms have been developed for several Run-Length Limited modulation codes. The results for a peak detection system show that Bi-Phase L code can be reliably employed up to a data rate of 5kbits/second/track. Development of a second system employing a TMS32025 and sampling detection permitted the utilisation of adaptive equalisation to slim the readback pulse. Application of conventional read equalisation techniques, that oppose inter-symbol interference, resulted in a 30% increase in performance. Further investigation shows that greater linear recording densities can be achieved by employing Partial Response signalling and Maximum Likelihood Detection. Partial response signalling schemes use controlled inter-symbol interference to increase recording density at the expense of a multi-level read back waveform which results in an increased noise penalty. Maximum Likelihood Sequence detection employs soft decisions on the readback waveform to recover this loss. The associated modulation coding techniques required for optimised operation of such a system are discussed. Two-dimensional run-length-limited (d, ky) modulation codes provide a further means of increasing storage capacity in multi-track recording systems. For example the code rate of a single track run length-limited code with constraints (1, 3), such as Miller code, can be increased by over 25% when using a 4-track two-dimensional code with the same d constraint and with the k constraint satisfied across a number of parallel channels. The k constraint along an individual track, kx, can be increased without loss of clock synchronisation since the clocking information derived by frequent signal transitions can be sub-divided across a number of, y, parallel tracks in terms of a ky constraint. This permits more code words to be generated for a given (d, k) constraint in two dimensions than is possible in one dimension. This coding technique is furthered by development of a reverse enumeration scheme based on the trellis description of the (d, ky) constraints. The application of a two-dimensional code to a high linear density system employing extended class IV partial response signalling and maximum likelihood detection is proposed. Finally, additional coding constraints to improve spectral response and error performance are discussed.Hewlett Packard, Computer Peripherals Division (Bristol

Design of a fully digital multi-level decision feedback equalization chip

Master'sMASTER OF ENGINEERIN