A three-stage ATM switch with cell-level path allocation

A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given-switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described

Design and analysis of a scalable terabit multicast packet switch : architecture and scheduling algorithms

Internet growth and success not only open a primary route of information exchange for millions of people around the world, but also create unprecedented demand for core network capacity. Existing switches/routers, due to the bottleneck from either switch architecture or arbitration complexity, can reach a capacity on the order of gigabits per second, but few of them are scalable to large capacity of terabits per second. In this dissertation, we propose three novel switch architectures with cooperated scheduling algorithms to design a terabit backbone switch/router which is able to deliver large capacity, multicasting, and high performance along with Quality of Service (QoS). Our switch designs benefit from unique features of modular switch architecture and distributed resource allocation scheme. Switch I is a unique and modular design characterized by input and output link sharing. Link sharing resolves output contention and eliminates speedup requirement for central switch fabric. Hence, the switch architecture is scalable to any large size. We propose a distributed round robin (RR) scheduling algorithm which provides fairness and has very low arbitration complexity. Switch I can achieve good performance under uniform traffic. However, Switch I does not perform well for non-uniform traffic. Switch II, as a modified switch design, employs link sharing as well as a token ring to pursue a solution to overcome the drawback of Switch 1. We propose a round robin prioritized link reservation (RR+POLR) algorithm which results in an improved performance especially under non-uniform traffic. However, RR+POLR algorithm is not flexible enough to adapt to the input traffic. In Switch II, the link reservation rate has a great impact on switch performance. Finally, Switch III is proposed as an enhanced switch design using link sharing and dual round robin rings. Packet forwarding is based on link reservation. We propose a queue occupancy based dynamic link reservation (QOBDLR) algorithm which can adapt to the input traffic to provide a fast and fair link resource allocation. QOBDLR algorithm is a distributed resource allocation scheme in the sense that dynamic link reservation is carried out according to local available information. Arbitration complexity is very low. Compared to the output queued (OQ) switch which is known to offer the best performance under any traffic pattern, Switch III not only achieves performance as good as the OQ switch, but also overcomes speedup problem which seriously limits the OQ switch to be a scalable switch design. Hence, Switch III would be a good choice for high performance, scalable, large-capacity core switches

Isochronets: a High-Speed Network Switching Architecture

Traditional switching techniques need hundred- or thousand-MIPS processing power within switches to support Gbit/s transmission rates available today. These techniques anchor their decision-making on control information within transmitted frames and thus must resolve routes at the speed in which frames are being pumped into switches. Isochronets can potentially switch at any transmission rate by making switching decisions independent of frame contents. Isochronets divide network bandwidth among routing trees, a technique called Route Division Multiple Access (RDMA). Frames access network resources through the appropriate routing tree to the destination. Frame structures are irrelevant for switching decisions. Consequently, Isochronets can support multiple framing protocols without adaptation layers and are strong candidates for all-optical implementations. All network-layer functions are reduced to an admission control mechanism designed to provide quality of service (QOS) guarantees for multiple classes of traffic. The main results of this work are: (1) A new network architecture suitable for high-speed transmissions; (2) An implementation of Isochronets using cheap off-theshelf components; (3) A comparison of RDMA with more traditional switching techniques, such as Packet Switching and Circuit Switching; (4) New protocols necessary for Isochronet operations; and (5) Use of Isochronet techniques at higher layers of the protocol stack (in particular, we show how Isochronet techniques may solve routing problems in ATM networks)

Vertical cavity surface emitting laser based optoelectronic asynchronous transfer mode switch

Abstract. Large broadband asynchronous transfer mode (ATM) switching nodes require novel hardware solutions that could benefit from the inclusion of optical interconnect technology, since electronic solutions are limited by pin out and by the capacitance/inductance of the interconnections. We propose, analyze and demonstrate a new three stage free space optical switch that utilizes vertical cavity surface emitting lasers (VCSELs) for the optical interconnections, a liquid crystal spatial light modulator (SLM) as a reconfigurable shutter and relatively simple optics for fan out and fan in. A custom complementary metal oxide semiconductor (CMOS) chip is required to introduce a time delay in the optical bit stream and to drive the VCSELs. Analysis shows that the switch should be scalable to 1024ϫ1024, which would require 2048 ϳ2 mW VCSELs

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

Designing a large scale switch interconnection architecture and a study of ATM scheduling algorithms.

by Yee Ka Chi.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 101-[106]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Large Scale Switch Interconnections --- p.2Chapter 1.1.2 --- Multichannel Switching and Resequencing --- p.6Chapter 1.1.3 --- Scheduling --- p.7Chapter 2 --- Hierarchical Banyan Switch Interconnection --- p.12Chapter 2.1 --- Introduction --- p.12Chapter 2.2 --- Switch Architecture --- p.13Chapter 2.3 --- Switch Operation --- p.19Chapter 2.3.1 --- Call Setup --- p.19Chapter 2.3.2 --- Cell Routing --- p.21Chapter 2.3.3 --- Fault Tolerance --- p.27Chapter 2.4 --- Call Blocking Analysis --- p.28Chapter 2.4.1 --- Dilated Banyan --- p.29Chapter 2.4.2 --- Dilated Benes Network --- p.30Chapter 2.4.3 --- HBSI --- p.30Chapter 2.5 --- Results and Discussions --- p.31Chapter 2.6 --- Summary --- p.37Chapter 3 --- Multichannel Switching and Resequencing --- p.40Chapter 3.1 --- Introduction --- p.40Chapter 3.2 --- Channel Assignment --- p.41Chapter 3.2.1 --- VC-Based Channel Allocation Mechanism --- p.41Chapter 3.2.2 --- Port-Based Channel Allocation Mechanism --- p.45Chapter 3.2.3 --- Trunk-Based Channel Allocation Mechanism --- p.46Chapter 3.3 --- Resequencer --- p.50Chapter 3.3.1 --- Resequencing Algorithm --- p.50Chapter 3.4 --- Results and Discussion --- p.55Chapter 3.5 --- Summary --- p.60Chapter 4 --- Scheduling --- p.62Chapter 4.1 --- Introduction --- p.62Chapter 4.2 --- Virtual Clock Scheduling (VCS) --- p.62Chapter 4.3 --- Gated Virtual Clock Scheduling (GVCS) --- p.70Chapter 4.4 --- Time-Priority Model --- p.75Chapter 4.5 --- Programmable Rate-based Scheduler (PRS) --- p.80Chapter 4.6 --- Integration with Resequencer --- p.83Chapter 4.7 --- Results and Discussions --- p.86Chapter 4.8 --- Summary --- p.96Chapter 5 --- Conclusion --- p.99Bibliography --- p.10

BMSN and SpiderNet as large scale ATM switch interconnection architectures.

by Kin-Yu Cheung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 64-[68]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Multistage Interconnection Architectures --- p.2Chapter 1.2 --- Interconnection Topologies --- p.4Chapter 1.3 --- Design of Switch Module-An Example of Multichannel Switch --- p.7Chapter 1.4 --- Organization --- p.8Chapter 1.5 --- Publication --- p.9Chapter 2 --- BMSN and SpiderNet: Two Large Scale ATM Switches --- p.13Chapter 2.1 --- Introduction --- p.13Chapter 2.2 --- Architecture --- p.14Chapter 2.2.1 --- Topology --- p.14Chapter 2.2.2 --- Switch Modules --- p.15Chapter 2.3 --- Routing --- p.17Chapter 2.3.1 --- VP/VC Routing --- p.18Chapter 2.3.2 --- VP/VC Routing Control --- p.22Chapter 2.3.3 --- Cell Routing --- p.23Chapter 2.3.4 --- Alternate Path Routing for Fault Tolerance --- p.24Chapter 2.4 --- SpiderNet --- p.25Chapter 2.5 --- Performance and Discussion --- p.26Chapter 2.5.1 --- BMSN vs SpiderNet --- p.26Chapter 2.5.2 --- Network Capacity --- p.29Chapter 2.6 --- Concluding Remarks --- p.30Chapter 3 --- Multichannel ATM Switching --- p.39Chapter 3.1 --- Introduction --- p.39Chapter 3.2 --- Switch Design --- p.40Chapter 3.3 --- Channel Allocation Algorithms --- p.41Chapter 3.3.1 --- VC-Based String Round Robin (VCB-SRR) Algorithm --- p.41Chapter 3.3.2 --- Implementation of the VCB-SRR Algorithm --- p.43Chapter 3.3.3 --- Channel Group Based Round Robin (CGB-RR) Algorithm --- p.50Chapter 3.3.4 --- Implementation of the CGB-RR Algorithm --- p.51Chapter 3.4 --- Performance and Discussion --- p.53Chapter 3.5 --- Concluding Remarks --- p.57Chapter 4 --- Conclusion --- p.62Bibliography --- p.6

Reconfiguration issues in a quasi-static packet switch.

by Man Wai-Hung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 62-66).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- General Types of Switch Architecture --- p.2Chapter 1.1.1 --- Input-Buffered Switch --- p.2Chapter 1.1.2 --- Output-Buffered Switch --- p.4Chapter 1.1.3 --- Crossbar-Based Switch --- p.4Chapter 1.1.4 --- Shared Buffer Memory Switch --- p.5Chapter 1.2 --- From Clos Network to Cross-path Switch --- p.6Chapter 1.3 --- Motivation and Organization --- p.12Chapter 2 --- Route Reconfiguration in Clos Network --- p.14Chapter 2.1 --- Connection Matrix in Clos Network --- p.15Chapter 2.2 --- Rearranging Central Modules in Clos Network --- p.18Chapter 2.3 --- Changing the Connection Matrix --- p.20Chapter 2.4 --- One Step Route Reconfiguration --- p.21Chapter 2.5 --- Closing Remarks --- p.25Chapter 3. --- Frame-Based Reconfiguration Scheme in Cross-Path Switch --- p.26Chapter 3.1 --- Route Assignment in Cross-Path Switch --- p.27Chapter 3.1.1 --- Requirement Matrix and Capacity Matrix --- p.27Chapter 3.1.2 --- Allocation Vector --- p.29Chapter 3.2 --- Progress Tracing in Cross-Path Switch --- p.30Chapter 3.3 --- Implementing Frame-Based Reconfiguration --- p.32Chapter 3.3.1 --- Recognizing Receiver Virtual Path --- p.33Chapter 3.3.2 --- Finding Donor Virtual Path --- p.34Chapter 3.4 --- Simulation Results --- p.36Chapter 3.4.1 --- Fixed Requirement Matrix --- p.36Chapter 3.4.2 --- Time-Varying Requirement Matrix --- p.38Chapter 3.5 --- Unfavourable Reconfigurations --- p.39Chapter 3.6 --- Closing Remarks --- p.41Chapter 4. --- Performance and Delay Tradeoff in Frame-Based Reconfiguration Scheme --- p.43Chapter 4.1 --- Service Curve and Cross-Path Switch --- p.44Chapter 4.2 --- Service Curve of Cross-Path Switch under Reconfiguration --- p.45Chapter 4.3 --- Impact of Reconfiguration Algorithms to Maximum Delay Increase --- p.48Chapter 4.4 --- Numerical Example --- p.56Chapter 4.5 --- Closing Remarks --- p.57Chapter 5. --- Conclusions and Future Researches --- p.59Chapter 5.1 --- Suggestions for Future Researches --- p.60Bibliography --- p.6