Mapping a mathematical expression onto a Montium ALU using GNU Bison

The Montium processing tile [1], [4] contains a number of complex ALUs which can perform many different operations in many different ways. In the Chameleon tool flow [2], it is necessary to automatically determine whether a certain mathematical expression can be mapped onto an ALU and to automatically generate an ALU configuration for this expression. This paper describes how the parser generator GNU Bison [5] is used to determine whether a mapping is possible and how Generalized LR Parsing [6] is used to cope with ambiguities and to generate all possible mappings of a specific expression onto an ALU

Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

Overview of the tool-flow for the Montium Processing Tile

This paper presents an overview of a tool chain to support a transformational design methodology. The tool can be used to compile code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Data Flow Graph (CDFG). A Control Dataflow Graph contains not only the dataflow operations (e.g. arithmetic or logical operations on data) but also control flow operations (e.g. operators for loop and if then else constructs). The CDFG is minimized using a set of behavior preserving transformations such as dependency analysis, common sub-expression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture

Static resource models for code generation of embedded processors

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ParaFPGA15 : exploring threads and trends in programmable hardware

The symposium ParaFPGA focuses on parallel techniques using FPGAs as accelerator in high performance computing. The green computing aspects of low power consumption at high performance were somewhat tempered by long design cycles and hard programmability issues. However, in recent years FPGAs have become new contenders as versatile compute accelerators because of a growing market interest, extended application domains and maturing high-level synthesis tools. The keynote paper highlights the historical and modern approaches to high-level FPGA and the contributions cover applications such as NP-complete satisfiability problems and convex hull image processing as well as performance evaluation, partial reconfiguration and systematic design exploration