PONDER - A Real time software backend for pulsar and IPS observations at the Ooty Radio Telescope

This paper describes a new real-time versatile backend, the Pulsar Ooty Radio Telescope New Digital Efficient Receiver (PONDER), which has been designed to operate along with the legacy analog system of the Ooty Radio Telescope (ORT). PONDER makes use of the current state of the art computing hardware, a Graphical Processing Unit (GPU) and sufficiently large disk storage to support high time resolution real-time data of pulsar observations, obtained by coherent dedispersion over a bandpass of 16 MHz. Four different modes for pulsar observations are implemented in PONDER to provide standard reduced data products, such as time-stamped integrated profiles and dedispersed time series, allowing faster avenues to scientific results for a variety of pulsar studies. Additionally, PONDER also supports general modes of interplanetary scintillation (IPS) measurements and very long baseline interferometry data recording. The IPS mode yields a single polarisation correlated time series of solar wind scintillation over a bandwidth of about four times larger (16 MHz) than that of the legacy system as well as its fluctuation spectrum with high temporal and frequency resolutions. The key point is that all the above modes operate in real time. This paper presents the design aspects of PONDER and outlines the design methodology for future similar backends. It also explains the principal operations of PONDER, illustrates its capabilities for a variety of pulsar and IPS observations and demonstrates its usefulness for a variety of astrophysical studies using the high sensitivity of the ORT.Comment: 25 pages, 14 figures, Accepted by Experimental Astronom

Implementation of a Direct-Imaging and FX Correlator for the BEST-2 Array

A new digital backend has been developed for the BEST-2 array at Radiotelescopi di Medicina, INAF-IRA, Italy which allows concurrent operation of an FX correlator, and a direct-imaging correlator and beamformer. This backend serves as a platform for testing some of the spatial Fourier transform concepts which have been proposed for use in computing correlations on regularly gridded arrays. While spatial Fourier transform-based beamformers have been implemented previously, this is to our knowledge, the first time a direct-imaging correlator has been deployed on a radio astronomy array. Concurrent observations with the FX and direct-imaging correlator allows for direct comparison between the two architectures. Additionally, we show the potential of the direct-imaging correlator for time-domain astronomy, by passing a subset of beams though a pulsar and transient detection pipeline. These results provide a timely verification for spatial Fourier transform-based instruments that are currently in commissioning. These instruments aim to detect highly-redshifted hydrogen from the Epoch of Reionization and/or to perform widefield surveys for time-domain studies of the radio sky. We experimentally show the direct-imaging correlator architecture to be a viable solution for correlation and beamforming.Comment: 12 pages, 17 figures, 2 tables, Accepted to MNRAS January 24, 2014, includes appendix diagram

A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Circuits and architectures for broadband spectrum channelizers with sub-band gain control

Broadband receiver architectures for full-band or concurrent multi-band reception of signals are required in several applications. One approach to implementing such receivers is a spectrum channelizer that employs a frequency-folded analog-to-digital converter (FF-ADC). The design downconverts and channelizes a broadband input signal into multiple sub-bands at baseband by employing the harmonics of non-overlapping rectangular clocks. The downconverted and aliased baseband signal in each path is digitized by a baseband ADC, referred to as a sub-ADC below, that operates with a sampling rate that is lower than the Nyquist sampling rate set by the full bandwidth of the input signal. Sub-band separation is performed through digital harmonic rejection (HR) and image rejection (IR). The design operates similar to a time-interleaved ADC, except that it significantly reduces the bandwidth requirement of the samplers. If rectangular pulse waveforms are used in the FF-ADC down-converter, all sub-bands experience nearly equal gain during frequency down-conversion. Since all sub-bands are aliased to baseband before they are separated in the digital domain, a sub-band with large relative power can reduce the sub-ADC dynamic range that is available for other sub-bands, in addition to appearing as a blocker for other sub-bands. The research presented in this dissertation addresses approaches to overcome this issue, by embedding sub-band gain control within an FF-ADC. Chapter 2 proposes an approach that employs pulse-width-modulated local oscillator (PWM-LO) waveforms in the polyphase paths of an FF-ADC for scaling individual sub-band signal levels at baseband before digitization. The PWM-LO waveforms, which directly drive switches in each path, can be used to vary the gain in each sub-band by varying the level of harmonics in the waveforms. This is achieved by controlling the pulse-widths of the PWM-LO waveforms. This design avoids the requirement for N ×N switch matrices and variable transconductance cells in prior demonstrated approaches. The proposed architecture makes it possible to vary the spectral response of the FF-ADC with low signal-path complexity. Prediction of pulse widths for the desired harmonic, and hence the gain profile across all sub-bands, is performed using an off-chip supervised learning approach employing a neural network. Chapter 3 presents the implementation of a spectrum channelizer employing the PWM-LO-based sub-band amplitude control. The design allows for scaling the relative gain of the sub-bands over a 20-dB range. This relaxes the compression performance of the channelizer baseband and the sub-ADC dynamic range in the presence of sub-bands with significantly higher signal levels. Gain control on individual sub-bands is performed by employing customized PWM-LO waveforms,where the PWM-LO pulses are generated using delay-locked loops (DLLs). The off-chip neural-network based learning technique for estimating the PWM symbol pulse widths required for setting the desired LO harmonic levels is described. A 1.6 GS/s spectrum channelizer IC is implemented in a 65-nm CMOS process to verify the architecture. The measured channelizer gain is 51.6-56.5 dB without gain scaling and provides a range of 37-59 dB with PWM-LO gain control. Gain-scaling at a specific harmonic improves blocker compression in an unattenuated sub-band from -34 dBm to -16 dBm. The in-band gain compression with gain-scaling also increases from -32 dBm to -17 dBm. Chapter 4 describes a spectrum channelizer that uses voltage-mode downconversion. The approach requires a single voltage-mode input amplifier to drive the downconversion switches. Frequency-folding and sub-band gain control are achieved in a single signal path. This contrasts with the current-mode approach that requires a main FF-ADC path and a separate auxiliary path for sub-band gain control. By avoiding the requirement for an auxiliary input path, the approach presented here significantly simplifies the signal chain with identical gain-scaling capability. The contributions of this research and scope for future related work are summarized in Chapter 5.Electrical and Computer Engineerin

Design and Applications of Minimally Invasive All-Pole Analog Filters

A new design technique for minimally invasive all-pole analog lowpass filters is introduced and the concept of minimally invasive filtering has been generalized for higher orders both in voltage-mode and current-mode operations. The proposed fully differential solution has minimal impact on the in-band signal in terms of added noise and nonlinearity, whereas it has comparable performance for out-of-band signals using smaller number of active devices. Extending the concept of current-mode minimally invasive filters, a novel baseband circuit with third order filtering has been designed, which has comparable linearity and noise with approximately half the power consumption when compared to the conventional solution. The proposed baseband circuit has a bandwidth of 10MHz, achieves 44dB rejection at 50MHz (40dB in post-layout simulations), low broad-band input impedance of 10.16ohm with a comparable noise and linearity at a lower power consumption when compared to a third order conventional circuit. The circuit has been designed in TSMC 130nm technology and is integrated with a broad-band receiver front-end including an LNA and a mixer

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver

Draadloze sensornetwerken worden meer en meer aangewend om verschillende soorten informatie te verzamelen. De locatie, waar deze informatie verzameld is, is een belangerijke eigenschap en voor sommige toepassingen, zoals het volgen van personen of goederen, zelfs de meest belangrijke en mogelijkmakende factor. Om de positie van een sensor te bepalen, is een technologie nodig die de afstand tot een gekend referentiepunt schat. Door verschillende afstandsmetingen te combineren, is het mogelijk de absolute locatie van de node te berekenen

A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.Ph.D.Committee Chair: Kim, Jongman; Committee Member: Kang, Sung Ha; Committee Member: Lee, Chang-Ho; Committee Member: Mukhopadhyay, Saibal; Committee Member: Tentzeris, Emmanouil

Caratterizzazione dello spazio architetturale di un amplificatore transconduttivo

Il presente lavoro di tesi affronta il problema della progettazione analogica a livello di sistema studiando un convertitore analogico/digitale di tipo pipeline ad elevate prestazioni in tecnologia CMOS a 0.13 um. Più specificamente, viene studiato l’amplificatore interstadio al fine di valutare l’ottimalità delle specifiche richieste nel progetto originale. Viene applicata una metodologia di progetto basata sulla esplorazione e caratterizzazione dello spazio architetturale di interesse, volta alla creazione di una libreria (Piattaforma Analogica) che racchiuda sia modelli di prestazioni dell’ amplificatore sia modelli comportamentali dello stesso da utilizzarsi per progettazione ad alto livello. Inizialmente, viene effettuata un’ analisi del primo stadio del convertitore pipeline volta a ricavare le specifiche del blocco amplificatore. La metodologia prevede un campionamento dello spazio delle prestazioni attraverso simulazione di configurazioni generate perturbando il progetto originale. Al fine di specificare lo spazio di campionamento, vengono ricavate delle relazioni che vincolano le dimensioni dei singoli dispositivi imponendo condizioni di polarizzazione, minimo guadagno e minima banda. Le relazioni vengono quindi manipolate al fine di ottenere uno schema valutativo, basato su MATLAB/Ocean, in grado di generare configurazioni casuali del circuito che rispettano le relazioni stesse. Un insieme di indici di prestazione viene ricavato dai dati delle simulazioni cui si ricorre dato lo scarso potere predittivo dei modelli analitici. Infatti, con le moderne tecnologie CMOS i parametri di merito sono legati alle dimensioni dei dispositivi attraverso equazioni non esprimibili in forma analitica. Gli indici di prestazione vengono utilizzati per la creazione di un modello di prestazione il cui scopo è di vincolare i parametri del modello comportamentale corrispondente a valori effettivamente ottenibili dall’architettura prescelta. Tale modello di prestazione può essere utilizzato per selezionare, tramite ottimizzazione a livello di sistema, un insieme di specifiche ottime per l’amplificatore in esame