High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

On-chip probe metrology

The semiconductor market was valued at over $270 billion in 2007, with projections to continue steady growth [7]. Any manufacturing process of this volume is tightly controlled to ensure high efficiency, and improvements are readily sought after. Despite semiconductor fabrication process advancements allowing circuits to contain larger numbers of transistors in smaller package sizes, there has not been any significant change in the way these circuits interface with test systems before packaging. This limitation causes the area overhead occupied by circuit contacts, known as bond pads, to become increasingly costly. To amend the situation, VLSI designers have attempted to reduce bond pads size and pitch as much as possible while retaining reliable probing accuracy [15]. Currently, there is no standard solution to assess the accuracy of probe stations inline with wafer testing. As such, a balance must be struck between overhead cost of large bond pads and operational cost spent analyzing probe performance off-line. A feedback loop on probe card performance during wafer fabrication sort could allow plants to recalibrate probe cards before a yield drop is detected, thus improving yield and saving operational costs [26]. This thesis demonstrates a proof of concept design that offers a viable solution to perform probe metrology in-line with wafer-level circuit testing. A versatile circuit was designed and laid out that promises fine accuracy resolution of 3.21 μm, and fast test time of 1.25 ms per probe

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Development of a Traceable Atomic Force Microscope with Interferometer and Compensation Flexure Stage

Entwicklung eines ruckfuhrbaren Rasterkraftmikroskops auf der Basis von Interferometern und einer geregelten Einkorperfuhrung Abstrakt Rastersondenmikroskope, zu denen unter anderem Rastertunnelmikroskope (STM) und Rasterkraftmikroskope (AFM) gezahlt werden, werden an vielen Stellen in der Material- und Oberflachenforschung, der Halbleitertechnologie sowie der Biotechnologie angewendet. Sie sind zudem denkbare Werkzeuge der Nanotechnologien, so beispielsweise der Nanolithographie. Zudem konnen sie der Manipulation von Atomen und zur Nanometrologie dienen. Kommerzielle AFM bestehen unter anderem aus einem Laser, Photoempfanger, Regler, Piezoantriebssystem sowie einem Tastsystem. Dabei kommt den Piezoelementen des Antriebssystems besondere Bedeutung zu. Die von Piezoelementen bekannten Nachteile, wie Nichtlinearitat, Hysterese, Alterung, thermische Drift, Kriechen und Ubersprechen, konnen durchaus 20% der Messabweichungen bei Vorwartssteuerung verursachen. Daher sollten AFM, Metrologiestandards entsprechend, zur Reduzierung der Mesunsicherheit regelmasig ruckfuhrbar kalibriert werden. Das Ziel der vorliegenden Arbeit bestand in der Entwicklung eines ruckfuhrbaren Rasterkraftmikroskops (Traceable Atomic Force Microscope, TAFM) zum Einsatz als staatliches Normal zur ruckfuhrbaren Vermessung von Normalen im Nanometer- Bereich fur die taiwanesische Industrie. Das TAFM wurde als Kombination eines kommerziellen AFM, zwei Laserinterferometern, einer aktiv geregelten dreiachsigen Prazisionsfuhrung, einem Metrologierahmen aus Super-Invar, einer Schwingungsdampfung sowie einer temperaturgeregelten Umhausung konzipiert und aufgebaut. Zur Reduzierung des Abbe-Offsets wurden die Interferometer derart angeordnet, dass sich ihre virtuell verlangerten Messstrahlen im Antastpunkt des Cantilevers und damit direkt auf der Probenoberflache im Messpunkt schneiden. Eine einwandfreie Referenzbewegung des Systems wurde durch die eingesetzten Prazisionsfuhrungen sichergestellt, wahrend die direkte Ruckfuhrbarkeit auf die Definition der Langeneinheit ?Meter" durch den Einsatz von zwei Laser- Interferometern erreicht wurde. Die ermittelte erweiterte Messunsicherheit des TAFM fur die laterale Messung einer Lange von 292 nm betrugt bei einer statistischen Sicherheit von 95% unter Berucksichtigung von 29 Freiheitsgraden 2,5 nm. Da die ermittelte erweiterte Messunsicherheit fur laterale Langenmessungen noch nicht zufriedenstellend und die Ruckfuhrbarkeit in Richtung der Z-Achse nicht gewahrleistet ist, soll das TAFM verbessert werden, um perspektivisch eine Messunsicherheit von 0,5 nm in allen drei Messachsen zu erreichen. Dieses Ziel kann zunachst durch den Einbau eines weiteren Laserinterferometers zur Kalibrierung des Messystems der Z-Achse erreicht werden. Zusatzlich sollte die Umhausung statt auf einem Tisch auf dem schwingungsarmeren Boden platziert werden, was das Rauschen der Interferometer auf weniger als 5 nm reduzieren sollte. Ein verstarkter Metrologierahmen, die Verlagerung der Referenzspiegel vom AFM auf die Prazisionsfuhrung und verkurzte Messkreise, die Konstruktion aller Teile aus dem gleichen Material, ein symmetrischer mechanischer Aufbau und der Einsatz einer aktiven Temperaturregelung mit einer Temperaturstabilitat von 20¡Ó0.1 ¢XC sind weitere wichtige Schritte.Scanning Probe Microscopes (SPMs), generally including such instruments as Scanning Tunneling Microscopes (STMs) and Atomic Force Microscopes (AFMs), have been widely applied to measure engineering surfaces in a variety of fields, such as material sciences, semiconductor industry, and biotechnology. SPMs will also be a potential tool in nanotechnology, for example nanolithography, atom manipulation, and nanometrology. Normally, a commercial AFM consists of a laser, a photo-detector, a controller, a piezo-scanner, and a cantilever tip. The piezo-scanner is critical to the performance of AFMs. The intrinsic properties of piezo-scanners, for instance non-linearity, hysteresis, aging, thermal drift, creep, and coupling effect will result in measurement errors that may reach up to 20 % of the reading. To reduce major measurement errors mentioned above, an AFM should be periodically calibrated with a traceable standard. The goal of my research study was to design a state-of-the-art Traceable Atomic Force Microscope (TAFM) to be used as a primary realization of nanometer scale standards for Taiwan industry. The TAFM was composed of a commercial AFM, two laser interferometers, a 3-axis active compensation flexure stage, a super-Invar metrology frame, a vibration isolator, and a temperature-controlled enclosed box with circulating water. To eliminate the Abbe-offset, the surface-plane of specimens was arranged on the same plane-level to the laser beams emitted by interferometers. The compensation flexure stage was aimed to provide a perfect reference motion mechanism. To achieve the direct traceability to the definition of meter, two interferometers were added to the flexure stage. The TAFM was evaluated to have an expanded uncertainty of 2.5 nm at a confidence level of 95 % and 29 degrees of freedom for a nominal pitch value of 292 nm. Since the expanded uncertainty of pitch measurement is not satisfactory and there is no traceability in the Z direction. The TAFM needs to be improved to meet the requirement of an expanded uncertainty of no more than 0.5 nm at 95 % confidence level at all three axes. The requirement can be achieved by the following improvements: A laser interferometer is added to the flexure stage for Z-height calibration. To reduce the noise of laser interferometer to about 5 nm, the support of the enclosed box is moved from tabletop to the floor. The metrology frame is improved by changing the reference mirrors from AFM to flexure stage, thickening the super-Invar frame, shortening the structure loop and metrology loop, using one material, and realizing a symmetrical mechanism design. The passive temperature control is changed to active temperature control, which will approach an anticipative temperature stability of (20¡Ó0.1) ¢XC in the measuring volume

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Using statistical metrology to understand pattern-dependent ILD thickness variation in oxide CMP processes

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (leaves 46-47).by Rajesh Ramji Divecha.M.Eng

High-Performance Silicon Nanowire Electronics

This thesis explores 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications via the fabrication and testing of SiNW-based ring oscillators. Both SiNW surface treatments and dielectric annealing are reported for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV), high carrier mobilities (~269 cm2/V•s), and low subthreshold swing (~80 mV/dec). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs is explored as well. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications. A set of novel charge-trap non-volatile memory devices based on high-performance SiNW FETs are well investigated. These memory devices integrate Fe2O3 quantum dots (FeO QDs) as charge storage elements. A template-assisted assembly technique is used to align FeO QDs into a close-packed, ordered matrix within the trenches that separate highly aligned SiNWs, and thus store injected charges. A Fowler-Nordheim tunneling mechanism describes both the program and erase operations. The memory prototype demonstrates promising characteristics in terms of large threshold voltage shift (~1.3 V) and long data retention time (~3 × 106 s), and also allows for key components to be systematically varied. For example, varying the size of the QDs indicates that larger diameter QDs exhibit a larger memory window, suggesting the QD charging energy plays an important role in the carrier transport. The device temperature characteristics reveal an optimal window for device performance between 275K and 350K. The flexibility of integrating the charge-trap memory devices with the SiNW logic devices offers a low-cost embedded non-volatile memory solution. A building block for a SiNW-based field-programmable gate array (FPGA) is proposed in the future work.</p

Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

Ph.DDOCTOR OF PHILOSOPH