Video over DSL with LDGM Codes for Interactive Applications

Digital Subscriber Line (DSL) network access is subject to error bursts, which, for interactive video, can introduce unacceptable latencies if video packets need to be re-sent. If the video packets are protected against errors with Forward Error Correction (FEC), calculation of the application-layer channel codes themselves may also introduce additional latency. This paper proposes Low-Density Generator Matrix (LDGM) codes rather than other popular codes because they are more suitable for interactive video streaming, not only for their computational simplicity but also for their licensing advantage. The paper demonstrates that a reduction of up to 4 dB in video distortion is achievable with LDGM Application Layer (AL) FEC. In addition, an extension to the LDGM scheme is demonstrated, which works by rearranging the columns of the parity check matrix so as to make it even more resilient to burst errors. Telemedicine and video conferencing are typical target applications

Matching Generalized-Bicycle Codes to Neutral Atoms for Low-Overhead Fault-Tolerance

Despite the necessity of fault-tolerant quantum sys- tems built on error correcting codes, many popular codes, such as the surface code, have prohibitively large qubit costs. In this work we present a protocol for efficiently implementing a restricted set of space-efficient quantum error correcting (QEC) codes in atom arrays. This protocol enables generalized-bicycle codes that require up to 10x fewer physical qubits than surface codes. Additionally, our protocol enables logical cycles that are 2-3x faster than more general solutions for implementing space- efficient QEC codes in atom arrays. We also evaluate a proof-of-concept quantum memory hier- archy where generalized-bicycle codes are used in conjunction with surface codes for general computation. Through a detailed compilation methodology, we estimate the costs of key fault- tolerant benchmarks in a hierarchical architecture versus a state-of-the-art surface code only architecture. Overall, we find the spatial savings of generalized-bicycle codes outweigh the overhead of loading and storing qubits, motivating the feasibility of a quantum memory hierarchy in practice. Through sensitivity studies, we also identify key program-level and hardware-level features for using a hierarchical architecture

Massively parallel implementation of cyclic LDPC codes on a general purpose graphic processing unit

2009 IEEE Workshop On Signal Processing Systems (SiPS) Tampere, Finland 2009-10-07 ~ 2009-10-09Simulation of low-density parity-check (LDPC) codes frequently takes several days, thus the use of general purpose graphics processing units (GPGPUs) is very promising. However, GPGPUs are designed for compute-intensive applications, and they are not optimized for data caching or control management. In LDPC decoding, the parity check matrix H needs to be accessed at every node updating process, and the size of H matrix is often larger than that of GPU on-chip memory especially when the code-length is long or the weight is high. In this work, the parity check matrix of cyclic or quasi-cyclic LDPC codes is greatly compressed by exploiting the periodic property of the matrix. In our experiments, the Compute Unified Device Architecture (CUDA) of Nvidia is used. With the (1057, 813) and (4161, 3431) projective geometry (PG)–LDPC codes, the execution speed of the proposed method is more than twice of the reference implementations that do not exploit the cyclic property of the parity check matrices

Implementing and characterizing precise multi-qubit measurements

There are two general requirements to harness the computational power of quantum mechanics: the ability to manipulate the evolution of an isolated system and the ability to faithfully extract information from it. Quantum error correction and simulation often make a more exacting demand: the ability to perform non-destructive measurements of specific correlations within that system. We realize such measurements by employing a protocol adapted from [S. Nigg and S. M. Girvin, Phys. Rev. Lett. 110, 243604 (2013)], enabling real-time selection of arbitrary register-wide Pauli operators. Our implementation consists of a simple circuit quantum electrodynamics (cQED) module of four highly-coherent 3D transmon qubits, collectively coupled to a high-Q superconducting microwave cavity. As a demonstration, we enact all seven nontrivial subset-parity measurements on our three-qubit register. For each we fully characterize the realized measurement by analyzing the detector (observable operators) via quantum detector tomography and by analyzing the quantum back-action via conditioned process tomography. No single quantity completely encapsulates the performance of a measurement, and standard figures of merit have not yet emerged. Accordingly, we consider several new fidelity measures for both the detector and the complete measurement process. We measure all of these quantities and report high fidelities, indicating that we are measuring the desired quantities precisely and that the measurements are highly non-demolition. We further show that both results are improved significantly by an additional error-heralding measurement. The analyses presented here form a useful basis for the future characterization and validation of quantum measurements, anticipating the demands of emerging quantum technologies.Comment: 10 pages, 5 figures, plus supplemen

VLSI algorithms and architectures for non-binary-LDPC decoding

Tesis por compendio[EN] This thesis studies the design of low-complexity soft-decision Non-Binary Low-Density Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps). In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended Min-Sum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput. Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm2. The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million NAND gates) is increased in almost five times compared to other proposals from literature. The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF(64) the throughput is 1259Mbps occupying an area of 28.90 mm2. On the other hand, a decoder architecture is implemented on a Field Programmable Gate Array (FPGA) device achieving 630 Mbps for the high-rate (2304,2048) NB-LDPC code over GF(16). To the best knowledge of the author, these results constitute the highest ones presented in literature for similar codes and implemented on the same technologies.[ES] En esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps). En la primera parte de la tesis los principales aspectos concernientes a los códigos NB-LDPC son analizados, incluyendo un estudio de los principales cuellos de botella presentes en los algoritmos de decodificación convencionales basados en decisión blanda (QSPA, EMS, Min-Max y T-EMS) y sus correspondientes arquitecturas hardware. A pesar de las limitaciones del algoritmo T-EMS (alta complejidad en el procesador del nodo de chequeo de paridad (CN), congestión en el rutado debido al intercambio de mensajes entre procesadores y la incapacidad de implementar decodificadores para campos de Galois de orden elevado debido a la elevada complejidad), éste fue seleccionado como punto de partida para esta tesis debido a su capacidad para alcanzar altas velocidades. Tomando en cuenta las limitaciones identificadas en el algoritmo T-EMS, la segunda parte de la tesis incluye seis artículos con los resultados de la investigación realizada con la finalidad de mitigar las desventajas del algoritmo T-EMS, ofreciendo soluciones que reducen el área, la latencia e incrementando la velocidad comparado con propuestas previas de la literatura sin sacrificar la ganancia de codificación. Especificamente, cinco algoritmos de decodificación de baja complejidad han sido propuestos, introduciendo simplificaciones en diferentes partes del proceso de decodificación. Además, arquitecturas completas de decodificadores han sido diseñadas e implementadas en una tecnologia CMOS de 90nm consiguiéndose una velocidad mayor a 1Gbps con un área menor a 10 mm2, aumentando la velocidad en 120% y reduciendo el área en 53% comparado con previas implementaciones del algoritmo T-EMS para el código (837,726) implementado sobre campo de Galois GF(32). Las arquitecturas propuestas reducen el área del CN, latencia, número de mensajes intercambiados entre el nodo de comprobación de paridad (CN) y el nodo variable (VN) y el número de elementos de almacenamiento en el decodificador. Considerando que estas propuestas mejoran tanto el área comola velocidad, el parámetro de eficiencia (Mbps / Millones de puertas NAND) se ha incrementado en casi cinco veces comparado con otras propuestas de la literatura. Las mejoras en términos de área nos ha permitido implementar decodificadores NBLDPC sobre campos de Galois de orden elevado, lo cual no habia sido posible hasta ahora debido a la alta complejidad de los decodificadores anteriormente propuestos en la literatura. Por lo tanto, en esta tesis se presentan los primeros resultados incluyendo el emplazamiento y rutado para códigos de alta tasa sobre campos finitos de orden mayor a GF(32). Por ejemplo, para el código (1536,1344) sobre GF(64) la velocidad es 1259 Mbps ocupando un área de 28.90 mm2. Por otro lado, una arquitectura de decodificador ha sido implementada en un dispositivo FPGA consiguiendo 660 Mbps de velocidad para el código de alta tasa (2304,2048) sobre GF(16). Estos resultados constituyen, según el mejor conocimiento del autor, los mayores presentados en la literatura para códigos similares implementados para las mismas tecnologías.[CA] En esta tesi s'aborda l'estudi del disseny d'algoritmes de baixa complexitat per a la descodificació de codis de comprovació de paritat de baixa densitat no binaris (NB-LDPC), i les seues corresponents arquitectures per a descodificar codis d'alta taxa a altes velocitats (centenars de Mbps i Gbps). En la primera part de la tesi els principals aspectes concernent als codis NBLDPC són analitzats, incloent un estudi dels principals colls de botella presents en els algoritmes de descodificació convencionals basats en decisió blana (QSPA, EMS, Min-Max i T-EMS) i les seues corresponents arquitectures. A pesar de les limitacions de l'algoritme T-EMS (alta complexitat en el processador del node de revisió de paritat (CN), congestió en el rutat a causa de l'intercanvi de missatges entre processadors i la incapacitat d'implementar descodificadors per a camps de Galois d'orde elevat a causa de l'elevada complexitat), este va ser seleccionat com a punt de partida per a esta tesi degut a la seua capacitat per a aconseguir altes velocitats. Tenint en compte les limitacions identificades en l'algoritme T-EMS, la segona part de la tesi inclou sis articles amb els resultats de la investigació realitzada amb la finalitat de mitigar els desavantatges de l'algoritme T-EMS, oferint solucions que redueixen l'àrea, la latència i incrementant la velocitat comparat amb propostes prèvies de la literatura sense sacrificar el guany de codificació. Específicament, s'han proposat cinc algoritmes de descodificació de baixa complexitat, introduint simplificacions en diferents parts del procés de descodificació. A més, s'han dissenyat arquitectures completes de descodificadors i s'han implementat en una tecnologia CMOS de 90nm aconseguint-se una velocitat major a 1Gbps amb una àrea menor a 10 mm2, augmentant la velocitat en 120% i reduint l'àrea en 53% comparat amb prèvies implementacions de l'algoritme T-EMS per al codi (837,726) implementat sobre camp de Galois GF(32). Les arquitectures proposades redueixen l'àrea del CN, la latència, el nombre de missatges intercanviats entre el node de comprovació de paritat (CN) i el node variable (VN) i el nombre d'elements d'emmagatzemament en el descodificador. Considerant que estes propostes milloren tant l'àrea com la velocitat, el paràmetre d'eficiència (Mbps / Milions deportes NAND) s'ha incrementat en quasi cinc vegades comparat amb altres propostes de la literatura. Les millores en termes d'àrea ens ha permès implementar descodificadors NBLDPC sobre camps de Galois d'orde elevat, la qual cosa no havia sigut possible fins ara a causa de l'alta complexitat dels descodificadors anteriorment proposats en la literatura. Per tant, nosaltres presentem els primers reports després de l'emplaçament i rutat per a codis d'alta taxa sobre camps finits d'orde major a GF(32). Per exemple, per al codi (1536,1344) sobre GF(64) la velocitat és 1259 Mbps ocupant una àrea de 28.90 mm2. D'altra banda, una arquitectura de descodificador ha sigut implementada en un dispositiu FPGA aconseguint 660 Mbps de velocitat per al codi d'alta taxa (2304,2048) sobre GF(16). Estos resultats constitueixen, per al millor coneixement de l'autor, els millors presentats en la literatura per a codis semblants implementats per a les mateixes tecnologies.Lacruz Jucht, JO. (2016). VLSI algorithms and architectures for non-binary-LDPC decoding [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/73266TESISCompendi

Error Correction For Automotive Telematics Systems

One benefit of data communication over the voice channel of the cellular network is to reliably transmit real-time high priority data in case of life critical situations. An important implementation of this use-case is the pan-European eCall automotive standard, which has already been deployed since 2018. This is the first international standard for mobile emergency call that was adopted by multiple regions in Europe and the world. Other countries in the world are currently working on deploying a similar emergency communication system, such as in Russia and China. Moreover, many experiments and road tests are conducted yearly to validate and improve the requirements of the system. The results have proven that the requirements are unachievable thus far, with a success rate of emergency data delivery of only 70%. The eCall in-band modem transmits emergency information from the in-vehicle system (IVS) over the voice channel of the circuit switch real time communication system to the public safety answering point (PSAP) in case of a collision. The voice channel is characterized by the non-linear vocoder which is designed to compress speech waveforms. In addition, multipath fading, caused by the surrounding buildings and hills, results in severe signal distortion and causes delays in the transmission of the emergency information. Therefore, to reliably transmit data over the voice channels, the in-band modem modulates the data into speech-like (SL) waveforms, and employs a powerful forward error correcting (FEC) code to secure the real-time transmission. In this dissertation, the Turbo coded performance of the eCall in-band modem is first evaluated through the adaptive white Gaussian noise (AWGN) channel and the adaptive multi-rate (AMR) voice channel. The modulation used is biorthogonal pulse position modulation (BPPM). Simulations are conducted for both the fast and robust eCall modem. The results show that the distortion added by the vocoder is significantly large and degrades the system performance. In addition, the robust modem performs better than the fast modem. For instance, to achieve a bit error rate (BER) of 10^{-6} using the AMR compression rate of 7.4 kbps, the signal-to-noise ratio (SNR) required is 5.5 dB for the robust modem while a SNR of 7.5 dB is required for the fast modem. On the other hand, the fading effect is studied in the eCall channel. It was shown that the fading distribution does not follow a Rayleigh distribution. The performance of the in-band modem is evaluated through the AWGN, AMR and fading channel. The results are compared with a Rayleigh fading channel. The analysis shows that strong fading still exists in the voice channel after power control. The results explain the large delays and failure of the emergency data transmission to the PSAP. Thus, the eCall standard needs to re-evaluate their requirements in order to consider the impact of fading on the transmission of the modulated signals. The results can be directly applied to design real-time emergency communication systems, including modulation and coding

Error Correction For Automotive Telematics Systems

One benefit of data communication over the voice channel of the cellular network is to reliably transmit real-time high priority data in case of life critical situations. An important implementation of this use-case is the pan-European eCall automotive standard, which has already been deployed since 2018. This is the first international standard for mobile emergency call that was adopted by multiple regions in Europe and the world. Other countries in the world are currently working on deploying a similar emergency communication system, such as in Russia and China. Moreover, many experiments and road tests are conducted yearly to validate and improve the requirements of the system. The results have proven that the requirements are unachievable thus far, with a success rate of emergency data delivery of only 70%. The eCall in-band modem transmits emergency information from the in-vehicle system (IVS) over the voice channel of the circuit switch real time communication system to the public safety answering point (PSAP) in case of a collision. The voice channel is characterized by the non-linear vocoder which is designed to compress speech waveforms. In addition, multipath fading, caused by the surrounding buildings and hills, results in severe signal distortion and causes delays in the transmission of the emergency information. Therefore, to reliably transmit data over the voice channels, the in-band modem modulates the data into speech-like (SL) waveforms, and employs a powerful forward error correcting (FEC) code to secure the real-time transmission. In this dissertation, the Turbo coded performance of the eCall in-band modem is first evaluated through the adaptive white Gaussian noise (AWGN) channel and the adaptive multi-rate (AMR) voice channel. The modulation used is biorthogonal pulse position modulation (BPPM). Simulations are conducted for both the fast and robust eCall modem. The results show that the distortion added by the vocoder is significantly large and degrades the system performance. In addition, the robust modem performs better than the fast modem. For instance, to achieve a bit error rate (BER) of 10^{-6} using the AMR compression rate of 7.4 kbps, the signal-to-noise ratio (SNR) required is 5.5 dB for the robust modem while a SNR of 7.5 dB is required for the fast modem. On the other hand, the fading effect is studied in the eCall channel. It was shown that the fading distribution does not follow a Rayleigh distribution. The performance of the in-band modem is evaluated through the AWGN, AMR and fading channel. The results are compared with a Rayleigh fading channel. The analysis shows that strong fading still exists in the voice channel after power control. The results explain the large delays and failure of the emergency data transmission to the PSAP. Thus, the eCall standard needs to re-evaluate their requirements in order to consider the impact of fading on the transmission of the modulated signals. The results can be directly applied to design real-time emergency communication systems, including modulation and coding

Selected Papers from the First International Symposium on Future ICT (Future-ICT 2019) in Conjunction with 4th International Symposium on Mobile Internet Security (MobiSec 2019)

The International Symposium on Future ICT (Future-ICT 2019) in conjunction with the 4th International Symposium on Mobile Internet Security (MobiSec 2019) was held on 17–19 October 2019 in Taichung, Taiwan. The symposium provided academic and industry professionals an opportunity to discuss the latest issues and progress in advancing smart applications based on future ICT and its relative security. The symposium aimed to publish high-quality papers strictly related to the various theories and practical applications concerning advanced smart applications, future ICT, and related communications and networks. It was expected that the symposium and its publications would be a trigger for further related research and technology improvements in this field

Graph-based techniques for compression and reconstruction of sparse sources

The main goal of this thesis is to develop lossless compression schemes for analog and binary sources. All the considered compression schemes have as common feature that the encoder can be represented by a graph, so they can be studied employing tools from modern coding theory. In particular, this thesis is focused on two compression problems: the group testing and the noiseless compressed sensing problems. Although both problems may seem unrelated, in the thesis they are shown to be very close. Furthermore, group testing has the same mathematical formulation as non-linear binary source compression schemes that use the OR operator. In this thesis, the similarities between these problems are exploited. The group testing problem is aimed at identifying the defective subjects of a population with as few tests as possible. Group testing schemes can be divided into two groups: adaptive and non-adaptive group testing schemes. The former schemes generate tests sequentially and exploit the partial decoding results to attempt to reduce the overall number of tests required to label all members of the population, whereas non-adaptive schemes perform all the test in parallel and attempt to label as many subjects as possible. Our contributions to the group testing problem are both theoretical and practical. We propose a novel adaptive scheme aimed to efficiently perform the testing process. Furthermore, we develop tools to predict the performance of both adaptive and non-adaptive schemes when the number of subjects to be tested is large. These tools allow to characterize the performance of adaptive and non-adaptive group testing schemes without simulating them. The goal of the noiseless compressed sensing problem is to retrieve a signal from its lineal projection version in a lower-dimensional space. This can be done only whenever the amount of null components of the original signal is large enough. Compressed sensing deals with the design of sampling schemes and reconstruction algorithms that manage to reconstruct the original signal vector with as few samples as possible. In this thesis we pose the compressed sensing problem within a probabilistic framework, as opposed to the classical compression sensing formulation. Recent results in the state of the art show that this approach is more efficient than the classical one. Our contributions to noiseless compressed sensing are both theoretical and practical. We deduce a necessary and sufficient matrix design condition to guarantee that the reconstruction is lossless. Regarding the design of practical schemes, we propose two novel reconstruction algorithms based on message passing over the sparse representation of the matrix, one of them with very low computational complexity.El objetivo principal de la tesis es el desarrollo de esquemas de compresión sin pérdidas para fuentes analógicas y binarias. Los esquemas analizados tienen en común la representación del compresor mediante un grafo; esto ha permitido emplear en su estudio las herramientas de codificación modernas. Más concretamente la tesis estudia dos problemas de compresión en particular: el diseño de experimentos de testeo comprimido de poblaciones (de sangre, de presencia de elementos contaminantes, secuenciado de ADN, etcétera) y el muestreo comprimido de señales reales en ausencia de ruido. A pesar de que a primera vista parezcan problemas totalmente diferentes, en la tesis mostramos que están muy relacionados. Adicionalmente, el problema de testeo comprimido de poblaciones tiene una formulación matemática idéntica a los códigos de compresión binarios no lineales basados en puertas OR. En la tesis se explotan las similitudes entre todos estos problemas. Existen dos aproximaciones al testeo de poblaciones: el testeo adaptativo y el no adaptativo. El primero realiza los test de forma secuencial y explota los resultados parciales de estos para intentar reducir el número total de test necesarios, mientras que el segundo hace todos los test en bloque e intenta extraer el máximo de datos posibles de los test. Nuestras contribuciones al problema de testeo comprimido han sido tanto teóricas como prácticas. Hemos propuesto un nuevo esquema adaptativo para realizar eficientemente el proceso de testeo. Además hemos desarrollado herramientas que permiten predecir el comportamiento tanto de los esquemas adaptativos como de los esquemas no adaptativos cuando el número de sujetos a testear es elevado. Estas herramientas permiten anticipar las prestaciones de los esquemas de testeo sin necesidad de simularlos. El objetivo del muestreo comprimido es recuperar una señal a partir de su proyección lineal en un espacio de menor dimensión. Esto sólo es posible si se asume que la señal original tiene muchas componentes que son cero. El problema versa sobre el diseño de matrices y algoritmos de reconstrucción que permitan implementar esquemas de muestreo y reconstrucción con un número mínimo de muestras. A diferencia de la formulación clásica de muestreo comprimido, en esta tesis se ha empleado un modelado probabilístico de la señal. Referencias recientes en la literatura demuestran que este enfoque permite conseguir esquemas de compresión y descompresión más eficientes. Nuestras contribuciones en el campo de muestreo comprimido de fuentes analógicas dispersas han sido también teóricas y prácticas. Por un lado, la deducción de la condición necesaria y suficiente que debe garantizar la matriz de muestreo para garantizar que se puede reconstruir unívocamente la secuencia de fuente. Por otro lado, hemos propuesto dos algoritmos, uno de ellos de baja complejidad computacional, que permiten reconstruir la señal original basados en paso de mensajes entre los nodos de la representación gráfica de la matriz de proyección.Postprint (published version