177 research outputs found
High Performance Power Management Integrated Circuits for Portable Devices
abstract: Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application.
In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency.
The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies
Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC
allows various small and large electronic systems to be implemented in a single chip. This
approach enables the miniaturization of design blocks that leads to high density transistor
integration, faster response time, and lower fabrication costs. To reap the benefits of SOC
and uphold the miniaturization of transistors, innovative power delivery and power
dissipation management schemes are paramount. This dissertation focuses on on-chip
integration of power delivery systems and managing power dissipation to increase the
lifetime of energy storage elements. We explore this problem from two different angels:
On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce
parasitic effects, and allow faster and efficient power delivery for microprocessors. Power
gating techniques, on the other hand, reduce the power loss incurred by circuit blocks
during standby mode.
Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide
semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic
dependency on the dynamic switching power and a more than linear dependency on static
power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power
loss, the supply power should be reduced. A significant reduction in power dissipation
occurs when portions of a microprocessor operate at a lower voltage level. This reduction
in supply voltage is achieved via voltage regulators or converters. Voltage regulators are
used to provide a stable power supply to the microprocessor. The conventional off-chip
switching voltage regulator contains a passive floating inductor, which is difficult to be
implemented inside the chip due to excessive power dissipation and parasitic effects.
Additionally, the inductor takes a very large chip area while hampering the scaling process.
These limitations make passive inductor based on-chip regulator design very unattractive
for SOC integration and multi-/many-core environments. To circumvent the challenges,
three alternative techniques based on active circuit elements to replace the passive LC filter
of the buck convertor are developed. The first inductorless on-chip switching voltage
regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass
filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse
with modulation (PWM). The second approach is a supplementary design utilizing a hybrid
low drop-out scheme to lower the output ripple of the switching regulator over a wider
frequency range. The third design approach allows the integration of an entire power
management system within a single chipset by combining a highly efficient switching
regulator with an intermittently efficient linear regulator (area efficient), for robust and
highly efficient on-chip regulation.
The static power (Pstatic) or subthreshold leakage power (Pleak) increases with
technology scaling. To mitigate static power dissipation, power gating techniques are
implemented. Power gating is one of the popular methods to manage leakage power during
standby periods in low-power high-speed IC design. It works by using transistor based
switches to shut down part of the circuit block and put them in the idle mode. The efficiency
of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A
conventional sleep transistor circuit design requires an additional header, footer, or both
switches to turn off the logic block. This additional transistor causes signal delay and
increases the chip area. We propose two innovative designs for next generation sleep
transistor designs. For an above threshold operation, we present a sleep transistor design
based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit
operation, we implement a sleep transistor utilizing the newly developed silicon-on
ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability
to control the threshold voltage via bias voltage at the back gate makes both devices more
flexible for sleep transistors design than a bulk MOSFET. The proposed approaches
simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep
transistor, and improve power dissipation. In addition, the design provides a dynamically
controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio
๋ฉ๋ชจ๋ฆฌ ์ดํ๋ฆฌ์ผ์ด์ ์ ์ํ ๋น ๋ฅธ ๊ณผ๋ ์๋ต ์ฑ๋ฅ์ ๊ฐ์ง๋ ๋์งํธ ๋ฎ์ ๋๋กญ์์ ๋ ๊ทค๋ ์ดํฐ ์ค๊ณ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2023. 2. ์ ๋๊ท .In this dissertation, the design of a fast transient response digital low-dropout regulator (DLDO) applicable to next-generation memory systems is discussed. Recent technologies in memory systems mainly aim at high power density and fast data rate. Accordingly, the need for a power converter withstanding a large amount of load current change in a short period is increased. Accordingly, a solution for compensating for a voltage drop that causes significant damage to a memory data input/output is searched according to a periodic clock signal. With this situation, two structures that achieve fast transient response performance under the constraints of memory systems are proposed.
To mitigate the transient response degradation under slow external clock conditions, an adaptive two-step search algorithm with event-driven approaches DLDO is proposed. The technique solves the limitations of loop operation time dependent on slow external clocks through a ring-amplifier-based continuous-time comparator. Also, shift register is designed as a circular structure with centralized control of each register to reduce the cost. Finally, the remaining regulation error is controlled by an adaptive successive approximation algorithm to minimize the settling time. Fast recovery and settling time are shown through the measurement of the prototype chip implemented by the 40-nm CMOS process.
Next, a digital low dropout regulator for ultra-fast transient response is designed. A slope-detector-based coarse controller to detect, compensate, and correct load current changes occurring at every rising or falling edge of tens to hundreds of megahertz clocks is proposed. Compensation efficiency is increased by the method according to the degree of change in load voltage over time. Furthermore, the LUT-based shift register enables the fast loop response speed of the DLDO. Finally, a bidirectional latch-based driver with fast settling speed and high resolution are proposed. The prototype chip is implemented with a 40-nm CMOS process and achieves effective load voltage recovery through fast transient response performance even with low load capacitance.๋ณธ ๋
ผ๋ฌธ์ ์ฐจ์ธ๋ ๋ฉ๋ชจ๋ฆฌ ์์คํ
์ ์ ์ฉ ๊ฐ๋ฅํ ๋น ๋ฅธ ๊ณผ๋ ์๋ต ์ฑ๋ฅ์ ๊ฐ์ง๋ ๋์งํ ๋ฎ์ ๋๋กญ์์ ๋ ๊ทค๋ ์ดํฐ์ ์ค๊ณ์ ๋ํด ๊ธฐ์ ํ๋ค. ๋ฉ๋ชจ๋ฆฌ ์์คํ
์ ์ต๊ทผ ๊ธฐ์ ๋ค์ ๋์ ์ ๋ ฅ ๋ฐ๋์ ๋น ๋ฅธ ๋ฐ์ดํฐ ์๋๋ฅผ ์ฃผ๋ ๋ชฉํ๋ก ํ๋ฉฐ ์ด์ ๋ง์ถ์ด ๋จ๊ธฐ๊ฐ, ๋ง์ ์์ ๋ถํ ์ ๋ฅ ๋ณํ๋ฅผ ๊ฒฌ๋๋ ํ์ ์ปจ๋ฒํฐ์ ํ์์ฑ์ด ๋์์ง๊ณ ์๋ค. ์ด์ ์ฃผ๊ธฐ์ ์ธ ํด๋ฝ ์ ํธ์ ๋ฐ๋ผ ๋ฉ๋ชจ๋ฆฌ ๋ฐ์ดํฐ ์
์ถ๋ ฅ์ ์ ์๋ฏธํ ์์์ ๋ฐ์์ํค๋ ์ ์ ๊ฐํ๋ฅผ ๋ณด์ํ๋ ํด๊ฒฐ ๋ฐฉ์์ ํ์ํ๋ค. ์ด๋ฅผ ํตํด ๋ฉ๋ชจ๋ฆฌ ์์คํ
์ด ๊ฐ์ง๋ ์ ์ฝ์กฐ๊ฑด ํ์์ ๋น ๋ฅธ ๊ณผ๋ ์๋ต ์ฑ๋ฅ์ ๋ฌ์ฑํ๋ ๋ ๊ฐ์ง ๊ตฌ์กฐ๋ฅผ ์ ์ํ๋ค.
์ฒซ ๋ฒ์งธ ์์ฐ์ผ๋ก์, ๋๋ฆฐ ์ธ๋ถ ํด๋ฝ ์กฐ๊ฑด์์ ์ ๋ฐ๋๋ ๋์งํ ๋ฎ์ ๋๋กญ์์ ๋ ๊ทค๋ ์ดํฐ์ ๊ณผ๋ ์๋ต ์ฑ๋ฅ ์ ํ๋ฅผ ์ํ์ํค๊ธฐ ์ํ ์ด๋ฒคํธ ์ฃผ๋ ๋ฐฉ์์ ์ ์ํ ๋ ๋จ๊ณ ์์น ๊ธฐ์ ์ ์ ์ํ๋ค. ๋ณธ ๊ธฐ์ ์ ๋๋ฆฐ ์ธ๋ถํด๋ฝ์ ์์กดํ ๋ฃจํ ๋์ ์๊ฐ์ ํ๊ณ๋ฅผ ๊ณ ๋ฆฌ ์ฆํญ๊ธฐ ๊ธฐ๋ฐ ์ฐ์ ์๊ฐ ๋น๊ต๊ธฐ๋ฅผ ํตํด ํด๊ฒฐํ๋ค. ๋ํ ์๋ฆฌ ์ด๋ ๋ ์ง์คํฐ์ ๊ตฌํ์ ์๋ชจ๋๋ ๋น์ฉ์ ์ค์ด๊ณ ์ ๊ฐ ๋ ์ง์คํฐ์ ์ ์ด ์ฅ์น๋ฅผ ์ค์์ผ๋ก ์ง์ ์ํจ ์ํํ ๊ตฌ์กฐ๋ก ์ค๊ณ๋์๋ค. ๋ง์ง๋ง์ผ๋ก ๋จ์์๋ ์กฐ์ ์๋ฌ๋ ์ ์๋ฐฉ์์ ์ถ์ฐจ ๋น๊ตํ ์๊ณ ๋ฆฌ์ฆ์ผ๋ก ์ ์ดํ์ฌ ๊ต์ ์ ํ์ํ ์๊ฐ์ ์ต์ํํ์๋ค. 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋ ํ๋กํ ํ์
์นฉ์ ์ธก์ ์ ํตํด ๋ถํ ์ ์์ ๋น ๋ฅธ ํ๋ณต ์๋์ ์ ์ ์๊ฐ์ ๋ณด์์ ํ์ธํ์๋ค.
๋ ๋ฒ์งธ ์์ฐ์ผ๋ก์, ์ด๊ณ ์ ๊ณผ๋ ์๋ต ํ๊ฒฝ์ ์ ํฉํ ๋์งํธ ๋ฎ์ ๋๋กญ์์ ๋ ๊ทค๋ ์ดํฐ๊ฐ ์ค๊ณ๋์๋ค. ์์ญ~์๋ฐฑ ๋ฉ๊ฐํค๋ฅด์ฏ ํด๋ฝ์ ์์น ๋๋ ํ๊ฐ ์ฃ์ง๋ง๋ค ๋ฐ์ํ๋ ๋ถํ ์ ๋ฅ ๋ณํ๋ฅผ ํ์งํ๊ณ ๋ณด์ํ๊ณ ์ ์ ํ๊ธฐ ์ํด ๊ธฐ์ธ๊ธฐ ํ์ง๊ธฐ ๊ธฐ๋ฐ coarse ์ ์ด๊ธฐ ๊ธฐ์ ์ ์ ์ํ๋ค. ์๊ฐ์ ๋ฐ๋ฅธ ๋ถํ ์ ์ ๋ณํ์ ์ ๋์ ๋ฐ๋ผ ์ฐจ๋ฑ ๋ณด์ํ๋ ์๊ณ ๋ฆฌ์ฆ์ ์ ์ฉํจ์ผ๋ก์จ ๋ณด์ ํจ์จ์ ๋์๋ค. ๋์๊ฐ ์๋ํ ๊ธฐ๋ฐ ์๋ฆฌ์ด๋ ๋ ์ง์คํฐ๋ ๋ถํ ์ ๋ฅ ๊ณผ๋ ์ํ ์ดํ ๋์งํ ๋ ๊ทค๋ ์ดํฐ์ ๋น ๋ฅธ ๋ฃจํ ์๋ต ์๋๋ฅผ ๊ฐ๋ฅ์ผ ํ์๋ค. ๋ง์ง๋ง์ผ๋ก ๋จ์ ์กฐ์ ์๋ฌ๋ฅผ ์ ์ดํ๋๋ฐ ์์ด์ ๊ธฐ์กด ์๋ฆฌ์ด๋ ๋ ์ง์คํฐ ๋ฐฉ์์์ ๋ฒ์ด๋ ๋น ๋ฅธ ์๋ ด ์๋์ ๋์ ํด์๋๋ฅผ ๊ฐ์ง๋ ์๋ฐฉํฅ ๋์น ๊ธฐ๋ฐ ๋๋ผ์ด๋ฒ๊ฐ ์ ์๋์๋ค. ํด๋น ํ๋กํ ํ์
์นฉ์ 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋์์ผ๋ฉฐ, ๋ฎ์ ๋ถํ ์ถ์ ์ฉ๋์๋ ๋น ๋ฅธ ๊ณผ๋ ์๋ต ์ฑ๋ฅ์ ํตํด ํจ๊ณผ์ ์ธ ๋ถํ ์ ์ ํ๋ณต์ ์ด๋ฃจ์ด ๋ด์๋ค.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 VARIOUS TYPES OF LDO 4
1.2.1 ANALOG LDO VS. DIGITAL LDO 4
1.2.2 CAP LDO VS. CAP-LESS LDO 6
1.3 THESIS ORGANIZATION 8
CHAPTER 2 BACKGROUNDS ON DIGITAL LOW-DROPOUT REGULATOR 9
2.1 BASIC DIGITAL LOW-DROPOUT REGULATOR 9
2.2 FAST TRANSIENT RESPONSE LOW-DROPOUT REGULATOR 12
2.2.1 RESPONSE TIME 13
2.2.1 SETTLING TIME 20
2.3 VARIOUS METHODS FOR IMPLEMENT FAST TRANSIENT DIGITAL LDO 21
2.3.1 EVENT-DRIVEN DIGITAL LDO 21
2.3.2 FEEDFORWARD CONTROL 23
2.3.3 COMPUTATIONAL DIGITAL LDO 25
2.4 DESIGN POINTS OF FAST TRANSIENT RESPONSE DIGITAL LDO 27
CHAPTER 3 A FAST DROOP-RECOVERY EVENT-DRIVEN DIGITAL LDO WITH ADAPTIVE LINEAR/BINARY TWO-STEP SEARCH FOR VOLTAGE REGULATION IN ADVANCED MEMORY 29
3.1 OVERVIEW 29
3.2 PROPOSED DIGITAL LDO 32
3.2.1 MOTIVATION 32
3.2.2 ALSC WITH TWO-DIMENSIONAL CIRCULAR SHIFTING REGISTER 36
3.2.3 SBSC WITH SUBRANGE SUCCESSIVE-APPROXIMATION REGISTER 39
3.2.4 STABILITY ANALYSIS 41
3.3 CIRCUIT IMPLEMENTATION 44
3.3.1 TIME-INTERLEAVED RING-AMPLIFIER-BASED COMPARATOR 44
3.3.2 ASYNCHRONOUS 2D CIRCULAR SHIFTING REGISTER 49
3.3.3 SUBRANGE SUCCESSIVE APPROXIMATION REGISTER 51
3.4 MESUREMENT RESULTS 54
CHAPTER 4 A FAST TRANSIENT RESPONSE DIGITAL LOW-DROPOUT REGULATOR WITH SLOPE-DETECTOR-BASED MULTI-STEP CONTROL FOR DIGITAL LOAD APPLICATION 62
4.1 OVERVIEW 62
4.2 PROPOSED DIGITAL LDO 64
4.2.1 MOTIVATION 64
4.2.2 ARCHITECTURE OF DIGITAL LDO 66
4.2.3 SLEW-RATE DEPENDENT COARSE-CONTROL LOOP 69
4.2.4 FINE-CONTROL LOOP 72
4.2.5 CONTROL FOR LOAD-TRANSIENT RESPONSE 74
4.3 CIRCUIT IMPLEMENTATION 77
4.3.1 COMPARATOR-TRIGGERED OSCILLATOR DESIGN 77
4.3.2 SLOPE DETECTOR DESIGN 81
4.3.3 LUT-BASED SHIFT REGISTER DESIGN 84
4.3.4 BI-DIRECTIONAL LATCH-BASED DRIVER DESIGN 86
4.4 MEASUREMENT(SIMULATION) RESULTS 90
CHAPTER 5 CONCLUSION 95
BIBLIOGRAPHY 97
์ด ๋ก 109๋ฐ
Proposal and design methodology of switching mode low dropout regulator for Bio-medical applications
The switching operation based low dropout (LDO) regulator utilizing on-off control is pre-sented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 A. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 m CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 A with the output ripple of 5 mVpp. The circuit area is 0.0173 mm2 in spite of using 0.6 m design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications
Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications
abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai
optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201
A Silicon Carbide Linear Voltage Regulator for High Temperature Applications
Current market demands have pushed the capabilities of silicon to the edge. High temperature and high power applications require a semiconductor device to operate reliably in very harsh environments. This situation has awakened interests in other types of semiconductors, usually with a higher bandgap than silicon\u27s, as the next venue for the fabrication of integrated circuits (IC) and power devices. Silicon Carbide (SiC) has so far proven to be one of the best options in the power devices field.
This dissertation presents the first attempt to fabricate a SiC linear voltage regulator. This circuit would provide a power management option for developing SiC processes due to its relatively simple implementation and yet, a performance acceptable to today\u27s systems applications. This document details the challenges faced and methods needed to design and fabricate the circuit as well as measured data corroborating design simulation results
Recommended from our members
High Efficiency Power Supplies for Multi-mode RF Power Amplifiers in Cellular Handset Applications
Cellular handset evolution requires the front end transmitter to support multiple 3G/4G bands for global roaming, and also to be backward compatible with the existing 2G (quad-band GSM/EDGE) network. The cost and size would be prohibitive if one power amplifier (PA) only supports one band or if multiple supplies are required for multiple PAs. Solutions of interest are based on multi-standard multi-band PAs (e.g. 2 multi-mode PAs instead of 8+ mode-specific PAs), and an efficient power supply that supports these multi-mode PAs.
The thesis starts with a study of PA supply architectures and DC-DC converters. A series architecture consisting of a boost converter followed by a buck converter has advantages of low-noise buck converter output, together with the ability to deliver full power at low battery voltages to extend the battery life. The buck converter presents a constant power load for the boost converter, which raises stability concerns. Small-signal control-to-output transfer functions are derived for peak or valley current mode controlled boost converter with a downstream regulated converter modeled as constant power load. It is shown how current mode control provides active damping to ensure stability and well-behaved dynamic response. Furthermore, it is shown how load current feedforward presents an effective way to improve power load transient response. Modeling and design approaches are validated by test circuit simulations, demonstrating stable operations using current mode control under constant power loads, and improved power step load transient response based on load current feedforward.
A buck/boost and LDO series architecture is proposed as the solution to address efficiency, linearity, noise and time mask requirements for the supplies supporting multi-standard, multi-band PAs. A monolithic integrated circuit (IC) has been designed and implemented in a standard 0.5๏ญ๏ฌ 5V CMOS process for supplying the multi-mode PAs. The buck/boost converter with wide output range delivers the peak efficiency of 92%. The power LDO has 1-4 MHz bandwidth, to support the GSM/EDGE/WCDMA time mask requirements and the polar EDGE operation. The test chip consumes the quiescent current 1.1 mA, and it delivers maximum 5 W output
Recommended from our members
Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies
CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds.
In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage.
In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail.
Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance.
Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA
A self-powered single-chip wireless sensor platform
Internet of thingsโ require a large array of low-cost sensor nodes, wireless connectivity, low power operation and system intelligence. On the other hand, wireless biomedical implants demand additional specifications including small form factor, a choice of wireless operating frequencies within the window for minimum tissue loss and bio-compatibility This thesis describes a low power and low-cost internet of things system suitable for implant applications that is implemented in its entirety on a single standard CMOS chip with an area smaller than 0.5 mm2. The chip includes integrated sensors, ultra-low-power transceivers, and additional interface and digital control electronics while it does not require a battery or complex packaging schemes. It is powered through electromagnetic (EM) radiation using its on-chip miniature antenna that also assists with transmit and receive functions. The chip can operate at a short distance (a few centimeters) from an EM source that also serves as its wireless link. Design methodology, system simulation and optimization and early measurement results are presented
- โฆ