A Novel Three-Point Modulation Technique for Fractional-N Frequency Synthesizer Applications

This paper presents a novel three-point modulation technique for fractional-N frequency synthesizer applications. Convention modulated fractional-N frequency synthesizers suffer from quantization noise, which degrades not only the phase noise performance but also the modulation quality. To solve this problem, this work proposes a three-point modulation technique, which not only cancels the quantization noise, but also markedly boosts the channel switching speed. Measurements reveal that the implemented 2.4 GHz fractional-N frequency synthesizer using three-point modulation can achieve a 2.5 Mbps GFSK data rate with an FSK error rate of only 1.4 %. The phase noise is approximately -98 dBc/Hz at a frequency offset of 100 kHz. The channel switching time is only 1.1 μs with a frequency step of 80 MHz. Comparing with conventional two-point modulation, the proposed three-point modulation greatly improves the FSK error rate, phase noise and channel switching time by about 10 %, 30 dB and 126 μs, respectively

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

DESIGN & IMPLEMENTATION OF FRACTIONAL – N FREQUENCY SYNTHESIZER

This research involves design & implementation of fractional – N frequency synthesizer with the following specifications: Frequency range (2350– 2750) MHz,Step size (1 kHz), Switching time 8.9 μs, & phase noise @10 kHz = -115dBc & spurious -69 dBc The third order Fractional –N technique was chosen to satisfy the design requirements. In this system the modulator placed on digital phase-locked loop to control the fractional value of the frequency division ratio thereby eliminating spurious and allowing good phase noise performance. The development in I.C. technology provides the simplicity in the design of fractional –N frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar,modulator & reference divider in single chip. Therefore our system consists of a single chip contains (low phase noise PFD, charge pump, prescalar, modulator & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The application of this synthesizer in frequency hopping systems, wireless transceivers ,GSM & radar because it has high switching speed ,low phase noise & low spurious level

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

Clock multiplication techniques for high-speed I/Os

Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored. First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz. Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB. Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively

An Analog Phase Interpolation Based Fractional-N PLL

A novel phase-locked loop topology is presented. Compared to conventional designs, this architecture aims to increase frequency resolution and reduce quantization noise while maintaining the fractional-N benefits of high bandwidth and low phase noise up-conversion. This is achieved utilizing a feedforward mechanism for offset cancellation from the integer-N frequency. The design is implemented in a 0.13μm CMOS process technology. A frequency resolution of 1.16Hz is achieved on a 5GHz differential delay cell VCO with a 100MHz reference oscillator. A ping-pong swallow counter topology alleviates pipeline latency to achieve 1-64 divide ratios. A digital pulse generator and nested phase-frequency detector provide tunable offset cancellation. A 5-bit current-steering DAC capable of 200ps pulses reduces output spurs. Theoretical calculations and Simulink modeling provides insight to the effects of non idealities in the system. Test structures and loop configurability are programmed via SPI interface through a custom GUI and prototype PCB

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201