Devenlopment of Compact Small Signal Quasi Static Models for Multiple Gate Mosfets

En esta tesis hemos desarrollado los modelos compactos explícitos de carga y de capacitancia adaptados para los dispositivos dopados y no dopados de canal largo (DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados) de un modelo unificado del control de carga derivado de la ecuación de Poisson. El esquema de modelado es similar en todos estos dispositivos y se adapta a cada geometría. Los modelos de la C.C. y de la carga son completamente compatibles. Las expresiones de la capacitancia se derivan del modelo de la carga. La corriente, la carga total y las capacitancias se escriben en términos de las densidades móviles de la carga en los extremos de fuente y drenador del canal. Las expresiones explícitas e infinitamente continuas se utilizan para las densidades móviles de la carga en la fuente y drenador. Las capacitancias modeladas demuestran el acuerdo excelente con las simulaciones numéricas 2D y 3D (SGT), en todos los regímenes de funcionamiento. Por lo tanto, el modelo es muy prometedor para ser utilizado en simuladores del circuito. Desafortunadamente, no mucho trabajo se ha dedicado a este dominio de modelado. Las cargas analíticas y las capacitancias, asociadas a cada terminal se prefieren en la simulación de circuito. Con respecto al SGT MOSFET, nuestro grupo fue el primero en desarrollar y publicar un modelo de las cargas y de las capacitancias intrínsecas, que es también analítico y explícito. La tesis es organizada como sigue: el capítulo (1) presenta el estado del arte, capítulo (2) el modelado compacto de los cuatro dispositivos: DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados; en el capítulo (3) estudiamos las capacitancias de fricción en MuGFETs. Finalmente el capítulo (4) resuma el trabajo hecho y los futuros objetivos que necesitan ser estudiados. Debido a la limitación de los dispositivos optimizados disponibles para el análisis, la simulación numérica fue utilizada como la herramienta principal del análisis. Sin embargo, cuando estaban disponibles, medidas experimentales fueron utilizadas para validar nuestros resultados. Por ejemplo, en la sección 2A, en el caso de DG MOSFETs altamente dopados podríamos comparar nuestros resultados con datos experimentales de FinFETs modelados como DG MOSFETs. La ventaja principal de este trabajo es el carácter analítico y explícito del modelo de la carga y de la capacitancia que las hace fácil de implementar en simuladores de circuitos. El modelo presenta los resultados casi perfectos para diversos casos del dopaje y para diversas estructuras no clásicas del MOSFET (los DG MOSFETs, los UTB MOSFETs y los SGTs). La variedad de las estructuras del MOSFET en las cuales se ha incluido nuestro esquema de modelado y los resultados obtenidos, demuestran su validez absoluta. En el capítulo 3, investigamos la influencia de los parámetros geométricos en el funcionamiento en RF de los MuGFETs. Demostramos el impacto de parámetros geométricos importantes tales como el grosor de la fuente y del drenador o, el espaciamiento de las fins, la anchura del espaciador, etc. en el componente parásito de la capacitancia de fricción de los transistores de la múltiple-puerta (MuGFET). Los resultados destacan la ventaja de disminuir el espaciamiento entre las fins para MuGFETs y la compensación entre la reducción de las resistencias parásitas de fuente y drenador y el aumento de capacitancias de fricción cuando se introduce la tecnología del crecimiento selectivo epitaxial (SEG). La meta de nuestro estudio y trabajo es el uso de nuestros modelos en simuladores de circuitos. El grupo de profesor Aranda, de la Universidad de Granada ha puesto el modelo actual de SGT en ejecución en el simulador Agilent ADS y buenos resultados fueron obtenidos.In this thesis we have developed explicit compact charge and capacitance models adapted for doped and undoped long-channel devices (doped Double-Gate (DG) MOSFETs, undoped DG MOSFETs, undoped Ultra-Thin-Body (UTB) MOSFETs and undoped Surrounding Gate Transistor (SGT)) from a unified charge control model derived from Poisson's equation. The modelling scheme is similar in all these devices and is adapted to each geometry. The dc and charge models are fully compatible. The capacitance expressions are derived from the charge model. The current, total charges and capacitances are written in terms of the mobile charge sheet densities at the source and drain ends of the channel. Explicit and infinitely continuous expressions are used for the mobile charge sheet densities at source and drain. As a result, all small signal parameters will have an infinite order of continuity. The modeled capacitances show excellent agreement with the 2D and 3D (SGT) numerical simulations, in all operating regimes. Therefore, the model is very promising for being used in circuit simulators. Unfortunately, not so much work has been dedicated to this modelling domain. Analytical charges and capacitances, associated with each terminal are preferred in circuit simulation. Regarding the surrounding-gate MOSFET, our group was the first to develop and publish a model of the charges and intrinsic capacitances, which is also analytic and explicit. The thesis is organized as follows: Chapter (1) presents the state of the art, Chapter (2) the compact modeling of the four devices: doped DG MOSFETs, undoped DG MOSFETs, undoped UTB MOSFETs and undoped SGT; in Chapter (3) we study the fringing capacitances in MuGFETs. Finally Chapter (4) summarizes the work done and the future points that need to be studied. Due to the limitation of available optimized devices for analysis, numerical simulation was used as the main analysis tool. However, when available, measurements were used to validate our results. The experimental part was realised at the Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la Neuve, Belgium. For example, in section 2A, in the case of highly-doped DG MOSFETs we could compare our results with experimental data from FinFETs modeled as DG MOSFETs. The main advantage of this work is the analytical and explicit character of the charge and capacitance model that makes it easy to implement in circuit simulators. The model presents almost perfect results for different cases of doping (doped/undoped devices) and for different non classical MOSFET structures (DG MOSFET, UTB MOSFETs and SGT). The variety of the MOSFET structures in which our modeling scheme has been included and the obtained results, demonstrate its absolute validity. In chapter 3, we investigate the influence of geometrical parameters on the RF performance in MuGFETs. We show the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET). Results highlight the advantage of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The goal of our study and work is the usage of our models in circuit simulators. This part, of implementing and testing our models of these multi gate MOSFET devices in circuit simulators has already begun. The group of Professor Aranda, from the University of Granada has implemented the SGT current model in the circuit simulator Agilent ADS and good results were obtained

Studies of short channel effects and Performance enhancement of nano-mosfet Based on multi-objective genetic algorithm Approach

The nano-scale devices face a major issue i.e Short Channel Effects, as a result of which the performance of the devices degrade. To enhance the performance of such devices, the SCEs should be reduced. This thesis contributes to enhance the performance of nano-scaled DG MOSFET by re-ducing the short channel effects. To approach towards the main objective of the thesis, a study has been done on analytical modeling of undoped symmetric DG MOSFET. Then, to get the picture of SCEs, the electrical parameters such as maximum Drain current(Ion),Leakage current(Ioff ), Sub threshold Swing (SS), Threshold voltage (Vth ), and Drain In-duced Barrier Lowering (DIBL) are analytically derived by solving 2-dimensional Poisson’s equation and the same are studied with the variation of design parameters such as L, tsi and tox. To validate such analytical models, SCEs are studied using ATLAS device simulator. Graded Cannel engineering techniques are used for reduction of SCEs. For further reduction or minimization of SCEs, a multi-objective optimization technique is used to enhance the accuracy with optimum design parameters. To validate the optimized structure, a simulated model is built with those optimized values of the design parameter and the performance of the device is compared with the existing result [32]

Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos

Design evolution of dual-material gate structure in cylindrical surrounding double-gate (CSDG) MOSFET using physics-based analytical modeling.

Doctoral Degree. University of KwaZulu- Natal, Durban.The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the fundamental component in present Micro and Nano-electronics device applications, such as switching, memory devices, communication devices, etc. MOSFET’s dimension has shrunk down following Moore’s law to attain high-speed operation and packing density integration. The scaling of conventional MOSFET has been the most prominent technological challenge in the past few years because the decreasing device dimensions increase the charge sharing from the source to the drain and that in turn give rises to the reduced gate-control over the channel, hot carrier induced degradation, and other SCEs. These undesired effects devaluate the device performance that compels optimum device design analysis for particular operating conditions. Therefore, several innovative device design/architectures, including Double-gate, FinFET, Surrounding gate MOSFET, etc., have been developed to mitigate device scaling challenges. Comprehensive research can be traced long for one such promising gate-all-around MOSFET, i.e., Cylindrical Surrounding Double-Gate (CSDG) MOSFET centrally hollow concentric structure, provides an additional internal control gate that improves the device electrical performance and offers easy accessibility. There have been several developments in terms of improvements, and applications of CSDG MOSFET have been practiced since after its evolution. This thesis’s work has been targeted to incorporate the gate material engineering in the CSDG structure after appropriate analysis of device physics-based modeling. In particular to the proposed structure, the electric field, pinch off capacitance, and after that thickness of the device parameters’ dependence have been mathematically derived from attaining the objective. Finally, a model based on a dual-material gate in CSDG MOSFET has been proposed. The electrical field in CSDG MOSFET has been analyzed in detail using a mathematical derivation of device physics, including the Surface-Potential, threshold voltage, and the gate-oxide capacitances of the internal and external part of the device. Further, the gate-oxide capacitance of CSDG MOSFET, particularly to the device pinch-off condition, has been derived. Since the device operation and analysis at the shorter channel are not similar to conventional long-channel MOSFETs, the depletion-width variation has been studied. The identified notion has been applied to derive the approximate numerical solution and silicon thickness inducing parameters for CSDG MOSFET to deploy the improvements in the device performance and novel design modifications. As the gate-material and gate-stack engineering is an alternative to overcome the device performance degradation by enhancing the charge transport efficiency, the CSDG MOSFET in a novel Dual-Metal Gate (DMG) structure design has been proposed and analyzed using the solution of 2D Poisson’s equations in the geometrical boundary conditions of the device. The model expressions obtained solution using the proposed structure has been compared with a single metal gate structure. Finally, it has been analyzed that the proposed model exhibits an excellent match with the analytical model. The obtained DMG device structure advances the carrier velocity and transport efficiency, resulting in the surface-potential profile caused by dissimilar gate metal work-function. The superior device characteristics obtained employing a dual-material structure in CSDG are promising and can reduce the threshold voltage roll-off, suppress the hot-carrier effects and SCEs

Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Subthreshold Modeling and Simulation of Silicon Nanotube Field Effect Transistors (SiNTFETs)

The MOS technologies with low device geometry and new architectures have accelerated the pace of computational technology. In order to uphold the challenges of scaling in sub 20nm regime and meet the aggressive specifications of ITRS, a novel and non-conventional devices have to intervene. So came the ultimate solution- Silicon Nanotube Field Effect Transistor (SiNTFET) with its unique architecture which enhances the electrical characteristics of the device and the performance. In this work, an analytical model of surface potential and threshold voltage for SiNTFETs are developed. The two dimensional poisson’s equation with a cylindrical coordinate system, has been evaluated to find surface potential. The concentration of the inversion charge has been evaluated in the channel in subthreshold regime using the surface potential equation and the Boltzmann equation. The threshold voltage of the device is stated as the gate voltage for which the calculated inversion charge equals the threshold charge. Assuming this definition, the threshold voltage of the device for different channel lengths is mathematically modeled. The effect on threshold voltage by the variation of physical parameters is detailed analysed. The physical parameters include gate oxide thickness, tube thickness and core thickness. The effects of DIBL and voltage roll-off are discussed. The model results are verified with the simulation results obtained by using device simulator, ATLASTM. It is observed that for short channel lengths (<30nm), the model values vary from the simulated data; that is because the quantum mechanical effects are neglected during modeling which are vital in those channel lengths. The objective of the work is to provide a basic model for threshold voltage of the SiNTFET. The electrical characteristics show that device has a potential to set a new technology road map and meet the ULSI application

Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications

Drift-Diffusion, Hydrodynamic and Monte Carlo simulations have been used in this work to simulate strained Si/SiGe devices for RF and CMOS applications. For numerical simulations of Si/SiGe devices, strain effects on the band structure of Si have been analyzed and analytical expressions are presented for parameters related to the bandgap and band alignment of Si/SiGe heterostructure. Optimization of n-type buried strained Si channel Si/SiGe MODFETs has been carried out in order to achieve high RF performance and high linearity. The impact of both lateral and vertical device geometries and different doping strategies has been investigated. The impact of the Ge content of the SiGe buffer on the performance of p-type surface channel strained Si/SiGe MOSFETs has been studied. Hydrodynamic device simulations have been used to assess the device performance of p-type strained Si/SiGe MOSFETs down to 35 nm gate lengths. Well-tempered strained Si MOSFETs with halo implants around the source/drain regions have been simulated and compared with those devices possessing only a single retrograde channel doping. The calibrations in respect of sub-100 nm Si and strained Si MOSFETs fabricated by IBM lead to a scaling study of those devices at 65 nm, 45 nm and 35 nm gate lengths. Using Drift-Diffusion simulations, ring oscillator circuit behaviour has been evaluated. Strained Si on insulator (SSOI) circuits have also been simulated and compared with strained Si circuits, Si circuits employing conventional surface channel MOSFETs along with SOI devices. Ensemble Monte Carlo simulations have been used to evaluate the device performance of n-type strained Si MOSFETs. A non-perturbative interface roughness scattering model has been used and validated by calibrating with respect to experimental mobility behaviour and device characteristics. The impact of interface roughness on the performance enhancement of strained Si MOSFETs has been investigated and evidence for reduced interface roughness scattering is presented, i.e., a smoother interface is suggested in strained Si MOSFETs. A 35 nm gate length Toshiba Si MOSFET has been simulated and the performance enhancement of 35 nm strained Si MOSFETs over the Toshiba Si device is predicted. Monte Carlo simulations are also employed to investigate the performance degradation due to soft-optical phonon scattering, which arises with the introduction of high-K gate dielectrics. Based on the device structures of the calibrated sub-100 nm n-type conventional and strained Si IBM MOSFETs, significant current degradation has been observed in devices with high-K gate dielectrics, HfO2 and Al2O3

Modelling and Simulation of Silicon Nanowire-Based Electron Devices for Computation and Sensing

Silicon Nanowires (SiNWs) are considered the fundamental component blocks of future nanoelectronics. Many interesting properties have gained them such a prominent position in the investigation in recent decades. Large surface-to-volume ratio, bio-compatibility, band-gap tuning are among the most appealing features of SiNWs. More importantly, in the ongoing process of dimension miniaturization, SiNWs compatibility with the existing and reliable silicon technology stands as a fundamental advantage. Consequently, the employment of SiNWs spred in several application fields: from computational logic where SiNWs are used to realize transistors, to bio-chemical sensing and nanophotonic applications. In this thesis work we concentrate our attention on the employment of SiNWs in computational logic and bio-chemical sensing. In particular, we aim at giving a contribution in the modelling and simulation of SiNW-based electron devices. Given the current intense investigation of new devices, the modelling of their electrical behaviour is strongly required. On one side, modelling procedures could give an insight on the physical phenomena of transport in nanometer scale systems where quantum effects are dominant. On the other side, the availability of compact models for actual devices can be of undeniable help in the future design process. This work is divided into two parts. After a brief introduction on Silicon Nanowires, the main fabrication techniques and their properties, the first part is dedicated to the modelling of Multiple-Independent Gate Transistors, a new generation of devices arisen from the composition of Gate-All-Around Transistors, finFETs and Double-Gate Transistors. Interesting applications resulting from their employment are Vertically-stacked Silicon Nanowire FETs, known to have an ambipolar behaviour, and Silicon Nanowire Arrays. We will present a compact numerical model for composite Multiple-Independent Gate Transistors which allows to compute current and voltages in complex structures. Validation of the model through simulation proves the accuracy and the computational efficiency of the resulting model. The second part of the thesis work is instead devoted to Silicon Nanowires for bio-chemical sensing. In this respect, major attention is given to Porous Silicon (PS), a non-crystalline material which demonstrated peculiar features apt for sensing. Given its not regular microscopic morphology made of a complex network of crystalline and non-crystalline regions, PS has large surface-to-volume ratio and a relevant chemical reactivity at room temperature. In this work we start from the fabrication of PS nanowires at Istituto Nazionale di Ricerca Metrologica in Torino (I.N.Ri.M.) to devise two main models for PSNWs which can be used to understand the effects of porosity on electron transport in these structures. The two modelling procedures have different validity regimes and efficiently take into account quantum effects. Their description and results are presented. The last part of the thesis is devoted to the impact of surface interaction of molecular compounds and dielectric materials on the transport properties of SiNWs. Knowing how molecules interact with silicon atoms and how the conductance of the wire is affected is indeed the core of SiNWs used for bio-chemical sensing. In order to study the phenomena involved, we performed ab-initio simulations of silicon surface interacting with SO2 and NO2 via the SIESTA package, implementing DFT code. The calculations were performed at Institut de Ciencia De Materials de Barcelona (ICMAB-CSIC) using their computational resources. The results of this simulation step are then exploited to perform simulation of systems made of an enormous quantity of atoms. Due to their large dimensions, atomistic simulations are not affordable and other approaches are necessary. Consequently, calculations with physics-based softwares on a larger spatial scale were adopted. The description of the obtained results occupies the last part of the work together with the discussion of the main theoretical insight gained with the conducted study

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions

Design and analytical performance of subthreshold characteristics of CSDG MOSFET.

Masters Degree. University of KwaZulu-Natal, Durban.The downscaling of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) devices have been the driving force for Nanotechnology and Very Large-Scale Integration (VLSI) systems. This is affirmed by Moore’s law which states that “The number of transistors placed in an Integrated Circuit (IC) or chip doubles approximately every two years”. The main objectives for the transistor scaling are: to increase functionality, switching speed, packing density and lower the operating power of the ICs. However, the downscaling of the MOSFET device is posed with various challenges such as the threshold roll-off, Drain Induced Barrier Lowing (DIBL), surface scattering, and velocity saturation known as Short Channel Effects (SCEs). To overcome these challenges, a cylindrically structured MOSFET is employed because it increases the switching speed, current flow, packing density, and provides better immunity to SCEs. This thesis proposes a Cylindrical Surrounding Double-Gate (CSDG) MOSFET which is an extended version of Double-Gate (DG) MOSFET and Cylindrical Surrounding-Gate (CSG) MOSFET in terms of form factor and current drive respectively. Furthermore, employing the Evanescent-Mode analysis (EMA) of a two-dimensional (2D) Poisson solution, the performance analysis of the novel CSDG MOSFET is presented. The channel length, radii Silicon film difference, and the oxide thickness are investigated for the CSDG MOSFET at the subthreshold regime. Using the minimum channel potential expression obtained by EMA, the threshold voltage and the subthreshold swing model of the proposed CSDG MOSFET are evaluated and discussed. The device performance is verified with various values of radii Silicon film difference and gate oxide thickness Finally, the low operating power and switching characteristics of the proposed CSDG MOSFET has been employed to design a simple CSDG bridge rectifier circuit for micropower electricity (energy harvester). Similar to the traditional MOSFETs, the switching process of CSDG MOSFET is in two operating modes: switch-ON (conduction of current between the drain and source) or switched-OFF (no conduction of current). However, unlike the traditional diode bridge rectifier which utilizes four diodes for its operation, the CSDG bridge rectifier circuits employs only two CSDGs (n-channel and p- channel) for its operation. This optimizes cost and improves efficiency. Finally, the results from the analyses demonstrate that the proposed CSDG MOSFET is a promising device for nanotechnology and self-micro powered device system application