Integrated Silicon Microwave and Millimeterwave Passive Components and Functions

Non

Extraction of transmission line parameters and effect of conductive substrates on their characteristics

Abstract: The paper presents the effect of conductive or lossy silicon (Si) substrates on the frequency-dependent distributed series impedance transmission line (TL) parameters, R(ω) and L(ω). The frequency variations of these parameters of the microstrip line for four different conductivities of Si substrate are observed and compared. Keysight Technologies (formerly Agilent’s Electronic Measurement Group) Advanced Design System is used for the electromagnetic simulations of the microstrip line structures. Scattering parameters (S-parameters) based equations are used to plot the variations of series impedance parameters as a function of frequency. Furthermore, this paper explains a complete method to extract various parameters related to a TL. The work extracts the parameters of a microstrip TL model provided with the GlobalFoundries 0.13 μm SiGe BiCMOS8HP process design kit up to 100 GHz

Modelling of interconnects in 3DIC based on layered green functions

As traditional CMOS scaling pace gradually slows down, three-dimensional (3D) integration offers another dimension of in the ”More-than-Moore” era. In this dissertation, a number of investigations were conducted to better model interconnects in 3D integrated circuit (IC), to evaluate electrical behavior including delay, power consumption, signal integrity (SI), and power integrity (PI) for 3D ICs. Partial Element Equivalent Circuit (PEEC) method with layered Green’s function is studied here, since it consumes less computational resources and provides better physical insight to model the interconnects in 3DIC for high-speed digital circuits. The work is organized as a series of papers. The first paper reviewed the fundamental methods to derive layered Green’s function in spectral domain using discrete complex image method (DCIM) and analyzed the effects of each Green function terms to model silicon interconnects. The second paper proposed a unique method to extract poles near branch cut in complex kp plane, to accurately extract surface wave effects. The last paper proposed a new equivalent circuit model for coplanar waveguide (CPW) structure on 3DIC. The silicon effects on series inductance were also studied by employing the modified Green functions with semiconductor images at a complex distance from spectral-domain analysis. --Abstract, page iii

Application of Maxwell-Wagner polarisation in monolithic technologies

Imperial Users onl

Modeling and characterization of on-chip interconnects, inductors and transformers

Ph.DNUS-SUPELEC JOINT PH.D. PROGRAMM

CMOS MESFET Cascode Amplifiers for RFIC Applications

abstract: There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Recent Trends and Considerations for High Speed Data in Chips and System Interconnects

This paper discusses key issues related to the design of large processing volume chip architectures and high speed system interconnects. Design methodologies and techniques are discussed, where recent trends and considerations are highlighted

Inductors in high-performance silicon radio frequency integrated circuits : analysis, modeling, and design considerations

Spiral inductors are a key component of mixed-signal and analog integrated circuits (IC's). Such circuits are often fabricated using silicon-based technology, owing to the inherent low-cost and high volume production aspects. However, semiconducting substrate materials such as silicon can have adverse effects on spiral inductor performance due to the lossy nature of the material. Since the operating requirements of many high performance IC's demand reactive components that have high Quality Factor's (Q's), and are thus low loss devices, the need for accurate modeling of such structures over lossy substrate media is key to successful circuit design. The Q's of commonly available off-chip inductors are in the range of 50- 100 for frequencies ranging up to a few gigahertz. Since off-chip inductors must be connected through package pins, solder bumps, etc., which all contribute additional loss and thus lower the apparent Q of an external device, the typical on-chip Q requirement for a given RFIC design is generally lower than that for an off-chip spiral solution. However, a spiral inductor that was designed and fabricated originally in a low loss technology such as thin-film alumina may have substantially worse performance in regard to Q if it is used in a silicon-based technology, owing to the conductive substrate. For this reason, it is imperative that semiconducting substrate effects be accurately accounted for by any modeling effort for monolithic spirals in RFICs. This thesis presents a complete modeling solution for both single and multi-level spiral inductors over lossy silicon substrates, along with design considerations and methods for mitigation of the undesirable performance effects of semiconducting substrates. The modeling solution is based on Spectral Domain Approach (SDA) solutions for frequency dependent complex capacitive (i.e. both capacitance and conductance) parasitic elements combined with a quasi-magnetostatic field solution for calculation of the frequency dependent complex inductive (i.e. both inductance and resistance) terms. The effects of geometry and process variations are considered as well as the incorporation of Patterned Ground Shields (PGS) for the purpose of Q enhancement. Proposals for future extensions of this work are discussed in the concluding chapter