As traditional CMOS scaling pace gradually slows down, three-dimensional (3D) integration offers another dimension of in the ”More-than-Moore” era. In this dissertation, a number of investigations were conducted to better model interconnects in 3D integrated circuit (IC), to evaluate electrical behavior including delay, power consumption, signal integrity (SI), and power integrity (PI) for 3D ICs. Partial Element Equivalent Circuit (PEEC) method with layered Green’s function is studied here, since it consumes less computational resources and provides better physical insight to model the interconnects in 3DIC for high-speed digital circuits. The work is organized as a series of papers. The first paper reviewed the fundamental methods to derive layered Green’s function in spectral domain using discrete complex image method (DCIM) and analyzed the effects of each Green function terms to model silicon interconnects. The second paper proposed a unique method to extract poles near branch cut in complex kp plane, to accurately extract surface wave effects. The last paper proposed a new equivalent circuit model for coplanar waveguide (CPW) structure on 3DIC. The silicon effects on series inductance were also studied by employing the modified Green functions with semiconductor images at a complex distance from spectral-domain analysis. --Abstract, page iii
