Cycle time optimization by timing driven placement with simultaneous netlist transformations

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed

Survey of partitioning techniques in silicon compilation

In the silicon compilation design process, partitioning is usually the first problem to be investigated because partitioning algorithms form the backbone of many algorithms including: system synthesis, processor synthesis, floorplanning, and placement. In this survey, several partitioning techniques will be examined. In addition, this paper will review the partitioning algorithms used by synthesis systems at different design levels

A New Optimization Cost Model for VLSI Standard Cell Placement

In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results show that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool.published_or_final_versio

Standard Transistor Array (STAR). Volume 1: Placement technique

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties

Through-silicon-via management during 3D physical design: When to add and how many?

Abstract — In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger area than regular gates. In this paper, we address two critical aspects of TSV management in 3D designs. First, we address the problem of how many TSVs to add in a design. Since TSVs occupy significant silicon area, a general tendency has been to use a minimum number of TSVs in 3D circuits. We show that such an approach does not give us the best possible result. Second, we address the problem of TSV insertion. Because TSVs occupy silicon area, their location is decided during the placement stage of 3D design. However, we show that this is not the best possible stage for TSV insertion. We propose a change in the physical design flow for 3D integrated circuits to address the limitations of existing TSV placement methodology. All our algorithms are integrated with commercial tools, and our results are validated based on actual GDSII layouts. Our experimental results show the effectiveness of our methods. I

Component Rearrangement on Printed Wiring Boards to Maximize the Fundamental Natural Frequency

A methodology to attain the highest fundamental natural frequency of a printed wiring board by rearranging its components has been developed. A general twodimensional rearrangement algorithm is developed by which the rearrangement of the component-lead-board (CLB Introduction Integrated circuit technology has advanced rapidly in the past twenty years. The means to produce electronic equipment with high reliability and minimum overall cost has captured the attention of numerous researchers. Most of these researchers have been concerned with finding the optimal placement [1-6], minimum chip area Another important aspect of building reliable PWBs is to reduce the probability of failure due to mechanically generated motions, which can cause high relative displacement levels of the components and, consequently, high stress levels. These cyclic stress levels often lead to fatigue-induced cracked components and solder joints. One way to reduce the high cyclic stress is to subject the PWB to dynamic loadings whose frequency content is below the PWB's lowest natural frequency

A Finite Domain Constraint Approach for Placement and Routing of Coarse-Grained Reconfigurable Architectures

Scheduling, placement, and routing are important steps in Very Large Scale Integration (VLSI) design. Researchers have developed numerous techniques to solve placement and routing problems. As the complexity of Application Specific Integrated Circuits (ASICs) increased over the past decades, so did the demand for improved place and route techniques. The primary objective of these place and route approaches has typically been wirelength minimization due to its impact on signal delay and design performance. With the advent of Field Programmable Gate Arrays (FPGAs), the same place and route techniques were applied to FPGA-based design. However, traditional place and route techniques may not work for Coarse-Grained Reconfigurable Architectures (CGRAs), which are reconfigurable devices offering wider path widths than FPGAs and more flexibility than ASICs, due to the differences in architecture and routing network. Further, the routing network of several types of CGRAs, including the Field Programmable Object Array (FPOA), has deterministic timing as compared to the routing fabric of most ASICs and FPGAs reported in the literature. This necessitates a fresh look at alternative approaches to place and route designs. This dissertation presents a finite domain constraint-based, delay-aware placement and routing methodology targeting an FPOA. The proposed methodology takes advantage of the deterministic routing network of CGRAs to perform a delay aware placement

Diseño automático de sistemas digitales : métodos heurísticos para la colocación óptima de elementos

Tesis Univ. Complutense de Madrid, 1981.Sección Deptal. de Arquitectura de Computadores y Automática (Físicas)Fac. de Ciencias FísicasTRUEProQuestpu