In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results show that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool.published_or_final_versio

Cheung, PYS

Ko, WL

Tse, SK

Yeung, CSK

Yuen, CK

HKU Scholars Hub

Title A New Optimization Cost Model for VLSI Standard CellPlacementAuthor(s) Cheung, PYS; Yeung, CSK; Tse, SK; Yuen, CK; Ko, WLCitationThe 1997 IEEE International Symposium on Circuits andSystems Hong Kong, China, 9-12 June 1997. In IEEEInternational Symposium on Circuits and Systems Proceedings,1997, v. 3, p. 1708-1711Issued Date 1997URL http://hdl.handle.net/10722/46014Rights Creative Commons: Attribution 3.0 Hong Kong License1997 IEEE International Symposium on Circuits and Systems, June -- 9-12,1997, Hong Kong A New Optimization Cost Model for VLSI Standlard Cell Placement P. Y.S. Cheung, C.S. K. Yeung, S.K. Tse, C. K. Yuen and W. L. KO Electrical & Electronic Engineering, The University ofHong Kon,g Abstract -- In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire- length cost model[2][3][6] by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results shows that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool. I. INTRODUCTION The VLSI placement came as one of the earliest problems needed to be fully automated as circuitry complexity has been doubled every two years predicted by the Morre's law[5]. In the placement stage, location of an individual block is assigned on a rectangular image to facilitate routing. Interconnections to external leads, called pins, are made in a manner to satis@ various physical constraints in routing phase. It is ideally the case that a given placement will achieve 100% routing within a given area. However, we are unable to know whether a placement solution is satisfactory until a later routing stage. So, we propose a new objective function hoping that it will lead to a good solution in the final layout, i.e., a high routability result. A far simpler objective which most placement algorithms used is to minimize the total wire-length parameter over all possible assignment of the cells. The calculation of the total wire length is the summation of the estimated length of each net which is usually obtained fiom the half-perimeter bounding box model[6] or the minimum steiner tree of the nets[2]. Even then, the problem has been found NP-complete and in general can only solved sub-optimally using heuristics. Obviously, the abstract model above is hypothetical and by no means reflect the true final routing wire length and even the optimal solution bear little implication to the final layout. Moreover, the wire length model only focuses on the amount of wiring but do not consider where the distribution. As a result, it can lead congestion and routing failures. Such a situation is illustrated in 0-7803-3583-X/97 $10.00 01997 IEEE 1708 Figuxel. In this paper, we propose a new optimization cost model called Net Crossinm, which distinguishes itself by having impact on the quality of ihe routing phase and hopefully leading mom compact layout. We also extend the well- known simulated annealing standard cell placement algorithm with our new cost model. The remainder of this paper is organized as follows. We address standard definition and OY new optimization model in section 11. A new standard cell placement algorithm is presented in section III. Experimental results are discussed in Section IV and fmally, the conclusion and discussion are in section V. vertical gird, spacing-l unit vertical gird, spacing=l unit (a) Shorter wire length Two tracks required (b) Longer wire length One tracks required Fiprel  An example shows that Dlacement minimizes wire length can induce more area required for routing. TI. STANDARD DEFINITION AND OUR OPTIMIZATION MODEL The definition and notation are given as follows: Pi standard cell is defmed by an ordered tuple 6=( tl t:! . . .& )where a non-zero t, denotes an input or outlput tenminal on the horizontal boundary of the cell, and B zero t, denotes an unused terminal. The terminals are assumed to be lying on the equally- spaced vertical grids and the number of grids for a cell is simply the cardinal I 6 I = k which is then directly proportional to the cell width. IJie mirror 6 of a cell is a transformation on 6 by reversing the terminal ordering, i.e. N N 6 = ( tk . .tztl ) A st;mdard cell librarv I; = { 61,62, ... 6, } is a set of distinct cells and for notational N N N N  convenience, we dso define = { 6 6 2, 6 A 7 = ( y1 y2 . . .y,, )is ordered tuple where N yp E t; or yp E for each p. The size of a row is the summation of the individual cell: 1 y 1 = xply . Notice that the cells in a row may not be unique. A channel consists of an upper row a = ( al a2 ... a, ) and a lower row p = ( PI P2 ... &) With respect to a channel, terminal tJ in cell apJ ( or Pp, respectively ). Then the set of all terminals C is simply: C = { all apJ 's and all PpJ 's } where 1 ~ p s p ,  1 I j  < I  cl,, 1 or 1 I p ~ n ,  1 rj 5 I PPI A @ n E C specifies a set of terminals to be interconnected and a connectivity list N = { nl , n2 , . . . n, ) is a collection of nets. The following definitions related to OUT definitions of net crossings. A crossing represents the situation where two nets intersect when individually connected. This is shown in Figure2 below. 1 flmost mawin / a crossings e Finure2 Although minimizing the number of crossings among nets in a channel would be ideal, formulating an algorithm for such a complexity is basically unfeasible. It should be remembered that the module placement is a two-dimensional problem, e.g., in standard cell layout style, the layout area consists of many rows and just to compute the crossings number itself is far from trivial. Moreover, the actual number of crossings in a channel is still an unknown parameter while the locations and orientations of cells are not fixed. Rather then concentrating on the nets in a channel as a whole, we propose to narrow down the definition of the number of crossings x from the perspective of a cell. Figure3 illustrates the basic idea. Assuming that the shaded cell C with terminals (tl, tz . . . ts) is centered at the origin of the Cartesian Plane and five other cells are connected to each of the terminals as shown. In Figure3(a), no nets are crossed and so xc is simply zero optimally. This would not be so if cell C2 and C4 are interchanged and in this case xc become one as in Figure3P). 4 th ._.,___............ .__._.._.__.... 1 st I c2 I .._.............. ...__............... Figure3fi) As in Figure3, suppose that five cells C1 ... CS randomly placed around cell C, they can be partitioned into two ordered sets U and L ; those reside on the upper half of the plane (consisting the 4* and 3d quadrants) and those on the lower half plane(the 1' and the 2nd quadrants), both arranged in anti-clockwise. Referring to Figure3(a), U =  (Cd, C2 ) and L = (C&, C,). Notice that the order of the terminals in C connecting to U, .i.e.,(t&) in anti-clockwise, which follow the order of U, and similarly but on the other side, L follows the proper terminals order of C. However, this in not the case in Figure3, while U = (C, , C4 ) is on the contrary of the terminal order of C. It should be noted that a net with both sides of terminals on the same vertical grid line, as the situation in Figure 4, induces no net crossings with other nets. 1709 This net induces no net crossings with other nets. 0, x = 0 in this case. Circuit #modules hiinaryl 752 x-axis #nets f#p in #rows 904 5526 20 Figure4 Indeed, this can be proved to be a necessary and sufficient condition for xc = 0. Now given a placement configuration of all cells, the total number of net crossings xcan be computed by: x = &c , where c is the total number of cells. By minimizing the net crossings xc for each cell, the total number of net crossing x would also be minimized. Here, we look back the situation in Figurel, in l(a), x = 1 and half premier wire length is 4 while in l(b), x = 0 and wire length is 5. Moreover, we can see two advantages of our model over the traditional wire-length model. First, xc can always be made to less than one-half of the maximum value since a simple side-mirror operation on cell c reverse the order of the terminals connecting to c. Second, the theoretical lower bound for x is always zero if there is no multi-terminals net, while there is no such lower bound in the wire-length model. We can also observe that electrical equivalent swappable terminals can further reduced xc. So, our optimization model is also applicable to the following physical design process after placement, i.e. channel pin assignment and global routing. III. STANDARD CELL PLACEMENT ALGORITHM In this section, we extend the simulated annealing placement algorithm[7] by applyi’ng our optimization model described in section 11. The reason for such an extension is that we want to see the direct effect of our model and avoid the effect of the algorithm. Here is our extension. The standard cell placement algorithm consists of two stages. In stagel, modules are allowed to be moved and interchanged within the range limiter, which is a rectangular window and shrinks as the temperature decreases. When the temperature is reduced to a point at which the window size becomes too small to allow the modules to switch rows, stage 2 begins. First, all the modules overlaps are removed and then the annealing process continues with two operations: interchanges of adjacent modules and changes of a module’s orientation,. i.e. side-mirror of the module in x direction. In this stage, we apply our optjmization model -- net crossings x, as the objective fiction, instead of the half perimeters of the bounding rectangles of all the nets. Recauqe our definition of x is focused on the module as described above, it should be noted that we regard the two adjacent cells as “one module” and the interchange operation changes the terminals penmutation of “the module” as in FigureS. The calculation of x is the number of net crossings on “ this, modulle”. a “module” in the calculation U of X I cells a standard cell Figure5 IV EXPEMENTAL RESULTS We evaluated our optimization model and algorithm on two test benchmarks. The first set is two benchmark circuits from 1990 International Workshop on Layout Synthesis and the second is two real (circuits generated by Mentor GraphicsTM using VHDL. The parameters of the two test bench is shown in Table I and II respectively. Table ll The second set of test bench #modules #nets #rows 163 2 1867 6 E c u i t  I I I I I 16-bHALU I 369 I  I  I In the first test benchmark, an initial placement soliution generated by Min -cut algorithm[l][4] is improved by the Timberwolf standard cell placement algorithm with traditional half perimeter bounding box model and our extension in Section III. M e r  that, we use the AutoCellsTM platform to do global , detailed routing and chip tiling. We compare the final layout area as in Table III. We also compare the placement results which the full process generated by AutoCellsTM in Table IV. Table III. Lavout Area Comuarison. Traditional Primary1 Primary2 Model V.S. our model 1 Circuit [ Chip area I Chip area I Chip I traditional model OUT area 17.28 15.71 -9% extension reduced 61.72 53.67 -13% Circuit Table III. Layout Area Comuarison. AutoCellsm V.S. our model In the second test benchmark, we import our placement result to Mentor GraphicsTM platform to finish the layout process. We compare the final chip area to the full process by Mentor Graphicsm. The results are in Table IV. We also compare the vias in the layout in Table V. The technology we used is CMOSN 1.2 micro. Chip area Chip area Chip area Mentor our reduced 4-bit adder Graphicsm extension 659994 624438 -5% 16 bit ALU 3891810 3740028 -4% V. CONCLUSION In this paper, we propose a new optimization model, net crossings, for VLSI standard cell placement. Our model distinguishes itself from the traditional half perimeter bounding box wire-length model by having direct impact on the quality of the channel routing phase and leads more compact layout. We prove our claims by implementing our model with a simulated annealing standard cells placement algorithm. We also compare with Commercid Tools AutoCellP and Mentor GraphicsTM and our model and algorithm generate more compact layout in all cases. It is obvious that our optimization model can be applied to other layout style such as building blocks and mixed beside standard cell architecture. Moreover, it is also applicable to channel pin assignment and global routing problem. We believe that further refinement and modification on the model can lead more compact layout. Circuit REFERENCE [ 11 Breuer, M. A., “A class of min-cut placement algorithms,” in Proc. of the I4Ih Design Automation Con$, pp.284-290, 1977. [2] Hanan, M., “On Steiner’s problem with rectilinear distance,” SUM Journal on Applied Mathematics, vol. 14, n0.2, pp. 255-265, March 1966. [3] Hwang, F.K., “On Steiner minimal trees with rectilinear distance,” SLAM Journal on Applied Mathematics, vol. 30, no. 1, pp. 104- 114. January 1976. heuristic procedure for partitioning graphs,” Bell System Technical Journal, vol. 49, no. 2, pp. 291-307, February 1970. [5] R. N. Noyce, “Microelectronics”, Scientific American, 237:62-69, September 1977. [6] Schweikert, D.G., “A 2-dimensional placement algorithm for the layout of electrical circuits,” in Proc. of 13Ih Design Automation Con$, [4] Kemighan, B. W. and S. Lin, “An efficient pp. 408-416,1976. [7] C. Sechen, D. Braun, A. Sangiovanni Vincentelli, “ThunderBird: a complete standard cell layout package,” in IEEE Journal of Solid- State Circuits, vol. 23, no. 2, pp. 410- 420, April 1988. Vias by Viasby Vias Mentor our extension reduced 1711 4-bit adder 16-bit ALU Graphicsm 289 272 -6% 1761 1710 -3% 

A New Optimization Cost Model for VLSI Standard Cell Placement

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A New Optimization Cost Model for VLSI Standard Cell Placement

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