A Novel Ergodic Discrete Difference Equation Cochlear Model

In this paper, a novel hardware-efficient electronic circuit cochlear model, the dynamics of which are described by an ergodic cellular automaton, is presented. Based on theoretical and numerical analyses, a parameter setting method so that the presented model properly works as a cochlear model is proposed. It is shown that the presented cochlear model designed by the proposed parameter setting method can reproduce typical nonlinear sound processing functions of mammalian cochleae such as nonlinear compression, two-tone suppression and two-tone distortion products. Furthermore, the presented model is implemented by a field programmable gate array (FPGA) and its operations are validated by experiments. It is shown that the presented model is much more hardware-efficient (i.e., consumes many fewer circuits elements) compared to some other electronic circuit cochlear models

Neuromodulation of Neuromorphic Circuits

We present a novel methodology to enable control of a neuromorphic circuit in close analogy with the physiological neuromodulation of a single neuron. The methodology is general in that it only relies on a parallel interconnection of elementary voltage-controlled current sources. In contrast to controlling a nonlinear circuit through the parameter tuning of a state-space model, our approach is purely input-output. The circuit elements are controlled and interconnected to shape the current-voltage characteristics (I-V curves) of the circuit in prescribed timescales. In turn, shaping those I-V curves determines the excitability properties of the circuit. We show that this methodology enables both robust and accurate control of the circuit behavior and resembles the biophysical mechanisms of neuromodulation. As a proof of concept, we simulate a SPICE model composed of MOSFET transconductance amplifiers operating in the weak inversion regime.The research leading to these results has received funding from the European Research Council under the Advanced ERC Grant Agreement Switchlet n.67064

A Novel Frequency Based Current-to-Digital Converter with Programmable Dynamic Range

This work describes a novel frequency based Current to Digital converter, which would be fully realizable on a single chip. Biological systems make use of delay line techniques to compute many things critical to the life of an animal. Seeking to build up such a system, we are adapting the auditory localization circuit found in barn owls to detect and compute the magnitude of an input current. The increasing drive to produce ultra low-power circuits necessitates the use of very small currents. Frequently these currents need to accurately measured, but current solutions typically involve off-chip measurements. These are usually slow, and moving a current off chip increases noise to the system. Moving a system such as this completely on chip will allow for precise measurement and control of bias currents, and it will allow for better compensation of some common transistor mismatch issues. This project affords an extremely low power (100s nW) converter technology that is also very space efficient. The converter is completely asynchronous which yields ultra-low power standby operation [1]

Neuromorphic silicon neuron circuits

23 páginas, 21 figuras, 2 tablas.-- et al.Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.This work was supported by the EU ERC grant 257219 (neuroP), the EU ICT FP7 grants 231467 (eMorph), 216777 (NABAB), 231168 (SCANDLE), 15879 (FACETS), by the Swiss National Science Foundation grant 119973 (SoundRec), by the UK EPSRC grant no. EP/C010841/1, by the Spanish grants (with support from the European Regional Development Fund) TEC2006-11730-C03-01 (SAMANTA2), TEC2009-10639-C04-01 (VULCANO) Andalusian grant num. P06TIC01417 (Brain System), and by the Australian Research Council grants num. DP0343654 and num. DP0881219.Peer Reviewe

Synthesis of neuromorphic circuits with neuromodulatory properties

The field of neuromorphic engineering shows great promise in delivering novel devices inspired by biological principles that would undertake sensory and processing tasks with an unprecedented level of efficiency. In order to achieve that, engineers are required to understand and implement the many complex biological regulatory mechanisms that allow the nervous system to robustly operate and adapt over scales covering many orders of magnitude, while at the same time using unreliable and noisy components. As a step towards that, this thesis aims at discussing and implementing the principles of neuromodulation in neuromorphic hardware, mechanisms which allow neurons to change and regulate their behaviour through the continuous control of their internal currents. We discuss how neural dynamics and its modulation can be broken down into four essential feedback loops, and we introduce a simplified model of the neural membrane respecting this fundamental structure. We present a novel methodology for controlling the neuron's behaviour through the shaping of its I-V curves in distinct timescales, thus characterising the behaviour of the neural circuit through its input-output properties. We show how modulation of the feedback loops affects the behaviour, and importantly, captures the transition between spiking and bursting oscillatory regimes, two major signalling modes of neurons. We then show how the architecture can be easily implemented using well-known neuromorphic building blocks based on subthreshold MOSFET circuits. Finally, we discuss how the excitability switch captured by the model can be exploited in simple network settings, thus opening up the possibility for future research into novel architectures where the control of cellular properties is utilised to shape the global behaviour of the network

Analog and Neuromorphic computing with a framework on a reconfigurable platform

The objective of the research is to demonstrate energy-efficient computing on a configurable platform, the Field Programmable Analog Array (FPAA), by leveraging analog strengths, along with a framework, to enable real-time systems on hardware. By taking inspiration from biology, fundamental blocks of neurons and synapses are built, understanding the computational advantages of such neural structures. To enable this computation and scale up from these modules, it is important to have an infrastructure that adapts by taking care of non-ideal effects like mismatches and variations, which commonly plague analog implementations. Programmability, through the presence of floating gates, helps to reduce these variations, thereby ultimately paving the path to take physical approaches to build larger systems in a holistic manner.Ph.D

Intrinsically Evolvable Artificial Neural Networks

Dedicated hardware implementations of neural networks promise to provide faster, lower power operation when compared to software implementations executing on processors. Unfortunately, most custom hardware implementations do not support intrinsic training of these networks on-chip. The training is typically done using offline software simulations and the obtained network is synthesized and targeted to the hardware offline. The FPGA design presented here facilitates on-chip intrinsic training of artificial neural networks. Block-based neural networks (BbNN), the type of artificial neural networks implemented here, are grid-based networks neuron blocks. These networks are trained using genetic algorithms to simultaneously optimize the network structure and the internal synaptic parameters. The design supports online structure and parameter updates, and is an intrinsically evolvable BbNN platform supporting functional-level hardware evolution. Functional-level evolvable hardware (EHW) uses evolutionary algorithms to evolve interconnections and internal parameters of functional modules in reconfigurable computing systems such as FPGAs. Functional modules can be any hardware modules such as multipliers, adders, and trigonometric functions. In the implementation presented, the functional module is a neuron block. The designed platform is suitable for applications in dynamic environments, and can be adapted and retrained online. The online training capability has been demonstrated using a case study. A performance characterization model for RC implementations of BbNNs has also been presented