Design and Architecture of a Hardware Platform to Support the Development of an Avionic Network Prototype

Résumé en français La récente évolution des architectures des systèmes avioniques a permis la création de réseaux avioniques modulaire embarqués (IMA) et l’augmentation du nombre de systèmes embarqués numériques dans chaque avion. Cette transition vers une nouvelle génération d’avions plus électriques permet une réduction du poids et de la consommation énergétique des aéronefs et aussi des couts de production et d’entretien. Pour atteindre une réduction du poids encore plus poussée et une amélioration de la bande passante des réseaux utilisés, des technologies innovatrices ont récemment été adoptées : ARINC 825 et AFDX qui permettent en fait une réduction du câblage nécessaire pour réaliser le réseau embarqué.Dans le cadre du projet AVIO 402, qui inclus plusieurs sujets de recherche qui concernent aussi les capteurs et leur interface avec le système IMA, une nouvelle architecture a été proposée pour la réalisation du réseau utilisé pour le système de contrôle de vol. Cette architecture est basée sur des bus ARINC 825 locaux, connectés entre eux en utilisant un réseau AFDX qui offre une meilleure bande passante ; les ponts entre les deux protocoles et les modules qui connectent les nœuds au réseau ont une structure générique pour supporter des protocoles différents et aussi plusieurs types des capteurs et actionneurs. Pour une évaluation des performances et une analyse des défis de son implémentation, la réalisation d’un prototype du réseau proposé est requise par le projet. Dans ce mémoire, le développement d’une plateforme matérielle pour soutenir la réalisation de ce prototype est traité et trois modules fondamentaux du prototype ont été conçus sous forme de "IP core" pour être subséquemment intégrés dans l’architecture du réseau qui sera implémenté en utilisant des FPGA. Les trois systèmes sont le contrôleur du bus CAN, utilisé comme base pour l’implémentation du protocole ARINC 825, le "End System" AFDX et le commutateur nécessaires pour la réalisation d’un réseau AFDX. Dans la première partie de ce mémoire, les objectifs visés sont présentés et une analyse des spécifications des protocoles considérés est fournie, cela permet d’identifier les fonctionnalités qui doivent être incluses dans chaque système et de déterminer si des solutions pour leur implémentation ont déjà été publiées et peuvent être réutilisées. Ensuite, le développement de chaque système est présenté et les choix de conception sont expliqués afin de montrer comment les fonctionnalités requises par les spécifications des deux protocoles peuvent être implémentées pour mieux répondre aux nécessités du projet AVIO 402.----------Abstract The objective of the present project is to design three modules for a hardware platform that will support the implementation of an avionic network prototype based on the FPGA technology. The considered network has been conceived to reduce cabling weight and to improve the available bandwidth, and it exploits the recently introduced ARINC 825 and AFDX protocols. In order to support the implementation of both these protocols, a CAN bus controller, an AFDX End System, and an AFDX Switch have been designed. After an extensive review of the existing literature about the two related avionic protocols, a study of the existing solutions for CAN and Ethernet protocols, on which they are based, has been done as well to identify what knowledge and technology could be reused. Because they are very similar, a flexible CAN controller has been implemented in hardware instead of an ARINC 825 one in order to support both these technologies and in order to reduce the IP core size. A combined HW/SW approach has been preferred for the AFDX End System architecture to leverage an existing UDP/IP protocol stack and the Ethernet layer included in the Linux kernel has been modified to create a portable and configurable implementation of AFDX. Since various problems have been encountered to reproduce an ARINC 653 compliant environment on the embedded system, the suggested design has been ported in a PC. Finally, an original solution for the implementation of the AFDX switch fabric has been finally presented; a space-division switching architecture has been chosen and tailored to meet the AFDX specification. Hardware parallelism is exploited to reduce the latency introduced on each frame by filtering them concurrently. Input buffers have been duplicated to separate high from low priority traffics, further reducing latency of critical frames and creating a redundancy that reduce the possibility of packet loss. Packet scheduling and double queuing guarantee that all critical frames are forwarded before low priority ones.Keywords: Avionic Full-Duplex Switched Ethernet, AFDX, ARINC 664, ARINC 825, CAN, Avionic Data Networks, Ethernet Switch, FPGA

SYSTEM-ON-A-CHIP SOLUTION FOR PLUG AND PLAY NETWORKED SMART TRANSDUCERS

The IEEE 1451 standards define sets of common communication interfaces to standardize the connectivity of transducer to microprocessor, instrumentation systems, and networks. This thesis presents a single chip solution for these standards using Altera's Excalibur chip. All pertinent elements of the standard for the Transducer Interface Model (TIM) and Network Capable Application Processor (NCAP) were implemented using a combination of hardware (FPGA) and software. The total design takes advantage of the architecture provided by the Excalibur chip. Past solutions have only implemented the TIM and interfaced it to an NCAP using the digital communication protocol defined in the standard. This solution eliminates inter-chip communication. Rather, an on-chip parallel connection is established between the TIM and NCAP through a high performance bus

An FPGA-embedded oscilloscope based on the IEEE1451.0 Std.

Digital oscilloscopes are adopted in several areas of knowledge, in particular in electrical engineering, since they are fundamental for measuring and classifying electrical signals. Thanks to the proliferation of Field Programmable Gate Arrays (FPGAs), embedded instruments are currently an alternative solution to stand-alone and modular instruments, traditionally available in the laboratories. High performance, low cost and the huge flexibility to change functional characteristics, make embedded instruments an emerging solution for conducting electrical experiments. This paper describes the project and the implementation of a digital oscilloscope embedded in a FPGA. In order to facilitate their control, an innovative architecture is defined according to the IEEE1451.0 Std., which is typically used to develop the denominated smart transducers.info:eu-repo/semantics/publishedVersio

Arquitectura de nodo inteligente para redes de sensores inalámbricas y escalables: aplicaciones en monitorización ambiental

Las redes de sensores son actualmente una de las tecnologías emergentes de mayor progreso e interés, en particular aquellas que emplean sistemas de comunicación inalámbricas. La integración de estas redes a las infraestructuras y a diversos entornos asociados a una red inalámbrica de comunicación ha transformado drásticamente la forma en que los datos del entorno son adquiridos y procesados. Actualmente las redes de sensores son consideradas como uno los pilares principales en una nueva forma de percibir e interactuar con el mundo que nos rodea, proporcionando beneficios a la sociedad y mejorando la productividad de las industrias. El desafío planteado por la integración de nodos heterogéneos y diversas interfaces en una red de sensores, ha conducido al desarrollo de algunos estándares internacionales como el ISO/IEC/IEEE 21451-x. La característica principal que plantean estos estándares es la escalabilidad de la red desde el punto de vista de la heterogeneidad de los nodos y una capacidad ¿plug-and-play¿. Con la estandarización, se pretende abordar el problema de la gran diversidad de interfaces presentes en el mercado, a fin de determinar la mejor forma de interconexión entre redes de sensores heterogéneos. Sin embargo, la implementación del estándar ISO/IEC/IEEE 21451-x es complicada y no contempla las limitaciones en capacidad de los nodos, tales como bajo consumo de energía, capacidad de memoria y capacidad de procesamiento. Además, el estándar no contempla las arquitecturas reconfigurables, las cuales pueden ser muy útiles dada la diversidad de posibles aplicaciones de las redes de sensores inalámbricas. Es necesario, por lo tanto, consolidar el uso de un Framework para las arquitecturas de nodos sensoriales inalámbricas que contemple además de la heterogeneidad de los transductores, la inclusión de arquitecturas reconfigurables en los nodos sensores. El desarrollo de esta Tesis se orienta al diseño de una plataforma (Framework) que de soporte a las arquitecturas de nodos de sensores inalámbricos, facilitando su integración en una red inalámbrica. El trabajo de investigación consta de dos partes primordiales. La primera parte se centra en la definición del Framework basado en el estándar internacional ISO/IEC/IEEE 21451-x y en su utilización en diversas aplicaciones. La segunda parte plantea la utilización de arquitecturas reconfigurables en nodos de sensores inalámbricos, planteándose como aporte la modificación del datasheet electrónico definido en el estándar ISO/IEC/IEEE 214510 como una herramienta novedosa que estandariza el proceso de reconfiguración de cualquier nodo en una red de sensores inalámbricas. Como resultados de esta Tesis podemos indicar que: - Se ha propuesto un Framework para arquitecturas escalables de nodos en redes inalámbricas, basado en el estándar ISO/IEC/IEEE 214510. Este Framework plantea la integración del sensor inteligente, definido por la familia de estándares ISO/IEC/IEEE 21451-x, y sistema operativo para redes de sensores inalámbricas llamado TinyOS. La finalidad del Framework propuesto es incrementar la escalabilidad y la ubiquidad de los nodos, permitiendo el uso de sensores e interfaces heterogéneas en la red. El funcionamiento e interés de este Framework se ha probado en un sistema de monitorización de variables medio-ambientales diseñado para la vigilancia de reservas naturales. - Además, se ha planteado, asimismo, un nuevo método para la estandarización del proceso de reconfiguración de nodos asociados a redes de sensores inalámbricas. Para ello se ha propuesto la definición de un nuevo datasheet electrónico (TEDS) asociado al estándar ISO/IEC/IEEE 21450 con el que es posible reconfigurar el hardware de acondicionamiento de señales del nodo sensor. Este nuevo datasheet ha sido implementado y se ha probado en una red de monitorización de variables medio-ambientales, demostrando su interés y utilidad en aplicaciones reales

Arquitectura de nodo inteligente para redes de sensores inalámbricas y escalables: aplicaciones en monitorización ambiental

El desarrollo de esta Tesis se orienta al diseño de una plataforma (Framework) que de soporte a las arquitecturas de nodos de sensores inalámbricos, permitiendo su integración en una red inalámbrica.CONACYT – Consejo Nacional de Ciencia y Tecnologí

Self-adaptivity of applications on network on chip multiprocessors: the case of fault-tolerant Kahn process networks

Technology scaling accompanied with higher operating frequencies and the ability to integrate more functionality in the same chip has been the driving force behind delivering higher performance computing systems at lower costs. Embedded computing systems, which have been riding the same wave of success, have evolved into complex architectures encompassing a high number of cores interconnected by an on-chip network (usually identified as Multiprocessor System-on-Chip). However these trends are hindered by issues that arise as technology scaling continues towards deep submicron scales. Firstly, growing complexity of these systems and the variability introduced by process technologies make it ever harder to perform a thorough optimization of the system at design time. Secondly, designers are faced with a reliability wall that emerges as age-related degradation reduces the lifetime of transistors, and as the probability of defects escaping post-manufacturing testing is increased. In this thesis, we take on these challenges within the context of streaming applications running in network-on-chip based parallel (not necessarily homogeneous) systems-on-chip that adopt the no-remote memory access model. In particular, this thesis tackles two main problems: (1) fault-aware online task remapping, (2) application-level self-adaptation for quality management. For the former, by viewing fault tolerance as a self-adaptation aspect, we adopt a cross-layer approach that aims at graceful performance degradation by addressing permanent faults in processing elements mostly at system-level, in particular by exploiting redundancy available in multi-core platforms. We propose an optimal solution based on an integer linear programming formulation (suitable for design time adoption) as well as heuristic-based solutions to be used at run-time. We assess the impact of our approach on the lifetime reliability. We propose two recovery schemes based on a checkpoint-and-rollback and a rollforward technique. For the latter, we propose two variants of a monitor-controller- adapter loop that adapts application-level parameters to meet performance goals. We demonstrate not only that fault tolerance and self-adaptivity can be achieved in embedded platforms, but also that it can be done without incurring large overheads. In addressing these problems, we present techniques which have been realized (depending on their characteristics) in the form of a design tool, a run-time library or a hardware core to be added to the basic architecture

Intelligent Sensor Networks

In the last decade, wireless or wired sensor networks have attracted much attention. However, most designs target general sensor network issues including protocol stack (routing, MAC, etc.) and security issues. This book focuses on the close integration of sensing, networking, and smart signal processing via machine learning. Based on their world-class research, the authors present the fundamentals of intelligent sensor networks. They cover sensing and sampling, distributed signal processing, and intelligent signal learning. In addition, they present cutting-edge research results from leading experts

Fast Packet Processing on High Performance Architectures

The rapid growth of Internet and the fast emergence of new network applications have brought great challenges and complex issues in deploying high-speed and QoS guaranteed IP network. For this reason packet classication and network intrusion detection have assumed a key role in modern communication networks in order to provide Qos and security. In this thesis we describe a number of the most advanced solutions to these tasks. We introduce NetFPGA and Network Processors as reference platforms both for the design and the implementation of the solutions and algorithms described in this thesis. The rise in links capacity reduces the time available to network devices for packet processing. For this reason, we show different solutions which, either by heuristic and randomization or by smart construction of state machine, allow IP lookup, packet classification and deep packet inspection to be fast in real devices based on high speed platforms such as NetFPGA or Network Processors

Real-time video scene analysis with heterogeneous processors

Field-Programmable Gate Arrays (FPGAs) and General Purpose Graphics Processing Units (GPUs) allow acceleration and real-time processing of computationally intensive computer vision algorithms. The decision to use either architecture in any application is determined by task-specific priorities such as processing latency, power consumption and algorithm accuracy. This choice is normally made at design time on a heuristic or fixed algorithmic basis; here we propose an alternative method for automatic runtime selection. In this thesis, we describe our PC-based system architecture containing both platforms; this provides greater flexibility and allows dynamic selection of processing platforms to suit changing scene priorities. Using the Histograms of Oriented Gradients (HOG) algorithm for pedestrian detection, we comprehensively explore algorithm implementation on FPGA, GPU and a combination of both, and show that the effect of data transfer time on overall processing performance is significant. We also characterise performance of each implementation and quantify tradeoffs between power, time and accuracy when moving processing between architectures, then specify the optimal architecture to use when prioritising each of these. We apply this new knowledge to a real-time surveillance application representative of anomaly detection problems: detecting parked vehicles in videos. Using motion detection and car and pedestrian HOG detectors implemented across multiple architectures to generate detections, we use trajectory clustering and a Bayesian contextual motion algorithm to generate an overall scene anomaly level. This is in turn used to select the architectures to run the compute-intensive detectors for the next frame on, with higher anomalies selecting faster, higher-power implementations. Comparing dynamic context-driven prioritisation of system performance against a fixed mapping of algorithms to architectures shows that our dynamic mapping method is 10% more accurate at detecting events than the power-optimised version, at the cost of 12W higher power consumption