Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques

Electronic devices often operate in harsh environments which contain a variation of radiation sources. Radiation may cause different kinds of damage to proper operation of the devices. Their sources can be found in terrestrial environments, or in extra-terrestrial environments like in space, or in man-made radiation sources like nuclear reactors, biomedical devices and high energy particles physics experiments equipment. Depending on the operation environment of the device, the radiation resultant effect manifests in several forms like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL). TID effect causes an increase in the delay and the leakage current of CMOS circuits which may damage the proper operation of the integrated circuit. To ensure proper operation of these devices under radiation, thorough testing must be made especially in critical applications like space and military applications. Although the standard which describes the procedure for testing electronic devices under radiation emphasizes the use of worst case test vectors (WCTVs), they are never used in radiation testing due to the difficulty of generating these vectors for circuits under test. For decades, design for testability (DFT) has been the best choice for test engineers to test digital circuits in industry. It has become a very mature technology that can be relied on. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Surprisingly, however, radiation testing has not yet made use of this reliable technology. In this thesis, a novel methodology is proposed to extend the usage of DFT to generate WCTVs for delay failure in Flash based field programmable gate arrays (FPGAs) exposed to total ionizing dose (TID). The methodology is validated using MicroSemi ProASIC3 FPGA and cobalt 60 facility

A comprehensive comparison between design for testability techniques for total dose testing of flash-based FPGAs

Radiation sources exist in different kinds of environments where electronic devices often operate. Correct device operation is usually affected negatively by radiation. The radiation resultant effect manifests in several forms depending on the operating environment of the device like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL). CMOS circuits and Floating gate MOS circuits suffer from an increase in the delay and the leakage current due to TID effect. This may damage the proper operation of the integrated circuit. Exhaustive testing is needed for devices operating in harsh conditions like space and military applications to ensure correct operations in the worst circumstances. The use of worst case test vectors (WCTVs) for testing is strongly recommended by MIL-STD-883, method 1019, which is the standard describing the procedure for testing electronic devices under radiation. However, the difficulty of generating these test vectors hinders their use in radiation testing. Testing digital circuits in the industry is usually done nowadays using design for testability (DFT) techniques as they are very mature and can be relied on. DFT techniques include, but not limited to, ad-hoc technique, built-in self test (BIST), muxed D scan, clocked scan and enhanced scan. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Despite all these recommendations for DFT, radiation testing has not benefited from this reliable technology yet. Also, with the big variation in the DFT techniques, choosing the right technique is the bottleneck to achieve the best results for TID testing. In this thesis, a comprehensive comparison between different DFT techniques for TID testing of flash-based FPGAs is made to help designers choose the best suitable DFT technique depending on their application. The comparison includes muxed D scan technique, clocked scan technique and enhanced scan technique. The comparison is done using ISCAS-89 benchmarks circuits. Points of comparisons include FPGA resources utilization, difficulty of designs bring-up, added delay by DFT logic and robust testable paths in each technique

A Hardware Security Solution against Scan-Based Attacks

Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature

50 Years of Spaceflight with Fourier Transform Spectrometers (FTS) Built at NASA GSFC

Over the past 50 years, NASA Goddard Space Flight Center (GSFC) has been developing, building, testing and flying a series of Fourier Transform Spectrometers (FTS). This began with the IRIS instruments on the Earth-orbiting Nimbus satellites and progressed to more sophisticated designs optimized for interplanetary spacecraft sent to Mars and later to the outer solar system. Adaptions have been made over time, including progressively higher spectral resolution, sensitivity, numbers of detectors and complexity. Instrument operating temperatures have decreased to enable remote sensing of the cold giant planet systems. In this paper we describe the historical evolution of this instrument line, comparing and contrasting different aspects such as optical design and materials, detector types and data handling. We conclude by looking towards the future. At present the CIRS-Lite prototype is being tested at NASA GSFC for potential use on a future mission to the ice giants, Uranus and Neptune. Surpassing the previous performance of the Voyager IRIS instruments remains challenging, and new technologies that could enable these measurements are discussed

Efficient Modeling of an Array Antenna and Requirements for Maritime Mobile Reception of Meteorological Satellite Imagery

Wireless communication is an integral part of safety at sea. Direct broadcasts from public weather satellites on L- and X-band provide real-time weather observations and weather product dissemination to end users. These high-bandwidth broadcasts offer enhanced data throughput and require accurate pointing of high-gain antennas. An electronically-steered array antenna can provide high gain and rapid beam steering without moving parts, suitable for deployment on small vessels offshore. Figures of merit, such as array antenna gain and input impedance, vary with the beam steering angle as a consequence of mutual coupling between array elements. The electromagnetic design of an electronically-steered array antenna is more complex than a parabolic dish or a fixed broadside array, requiring an iterative development process and a computationally efficient method of simulating the array. This work addresses the validation of an efficient method for array simulation, a necessary first step in the design process of a deployable array. Starting with a small L-band subarray, a Fourier windowing method is applied to approximate the scan-dependent behavior of an electronically-steered array from an efficient numerical model in a periodic unit cell. Results are validated against experimental measurements of hardware prototypes and explicit numerical models of the subarray. The iterative design of antenna elements in an array environment and construction of a full-size array are left for future work

Efficient Modeling of an Array Antenna and Requirements for Maritime Mobile Reception of Meteorological Satellite Imagery

Wireless communication is an integral part of safety at sea. Direct broadcasts from public weather satellites on L- and X-band provide real-time weather observations and weather product dissemination to end users. These high-bandwidth broadcasts offer enhanced data throughput and require accurate pointing of high-gain antennas. An electronically-steered array antenna can provide high gain and rapid beam steering without moving parts, suitable for deployment on small vessels offshore. Figures of merit, such as array antenna gain and input impedance, vary with the beam steering angle as a consequence of mutual coupling between array elements. The electromagnetic design of an electronically-steered array antenna is more complex than a parabolic dish or a fixed broadside array, requiring an iterative development process and a computationally efficient method of simulating the array. This work addresses the validation of an efficient method for array simulation, a necessary first step in the design process of a deployable array. Starting with a small L-band subarray, a Fourier windowing method is applied to approximate the scan-dependent behavior of an electronically-steered array from an efficient numerical model in a periodic unit cell. Results are validated against experimental measurements of hardware prototypes and explicit numerical models of the subarray. The iterative design of antenna elements in an array environment and construction of a full-size array are left for future work

Test Strategies for Low Power Devices

Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing of these low-cost, low-power devices is a daunting task. Depending on the target application, there are stringent guidelines on the number of defective parts per million shipped devices. At the same time, since such devices are cost-sensitive, test cost is a major consideration. Since system-level power-management techniques are employed in these devices, test generation must be power-management-aware to avoid stressing the power distribution infrastructure in the test mode. Structural test techniques such as scan test, with or without compression, can result in excessive heat dissipation during testing and damage the package. False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss. This paper considers different aspects of testing low-power devices and some new techniques to address these problems.Design, Automation and Test in Europe (DATE \u2708), 10-14 March 2008, Munich, German

Hybrid Diagnosis Model To Determine Fault Isolation For Scan Chain Failure Analysis On 22nm Fabrication Process

With the rapid growth of Very Large Scale Integration (VLSI) in complex designs, there is high demand for Design for Testability (DFT). Vast study has proven that Scan based testing is achieving good test coverage with lower cost and smaller die area and is widely used in the industry. Scan chain fault diagnosis plays an important role as with the implementation of Scan based testing, it is reported that 10%-30% of defects in a Scan based design occurs within the Scan chain itself. Currently, there are three main types of stand-alone diagnosis models available, which are: software-based diagnosis, tester-based diagnosis and hardware-based diagnosis, where each has its disadvantages and limitations. In this project, the author proposed a hybrid Scan chain failure analysis technique that uses the proposed software-based diagnosis to obtain a list of possible failing suspect Scan cells, followed by the proposed tester-based diagnosis to further isolate the fault to a single failing device suspect. This proposed hybrid diagnosis algorithm ensures that Scan chain faults such as stuck-at and transition faults can be root-caused with lesser time and low complexity for both solid and marginal failures. Four case studies were successfully carried out to evaluate the proposed hybrid diagnosis algorithm on a 22nm fabrication process technology Device under Test (DUT) System-on-Chip (SOC) product, where the fault isolation was able to isolate a single failing device suspect for all four case studies, indicating a 100% fault isolation success rate

Zeeman Slowers for Strontium based on Permanent Magnets

We present the design, construction, and characterisation of longitudinal- and transverse-field Zeeman slowers, based on arrays of permanent magnets, for slowing thermal beams of atomic Sr. The slowers are optimised for operation with deceleration related to the local laser intensity (by the parameter $\epsilon$), which uses more effectively the available laser power, in contrast to the usual constant deceleration mode. Slowing efficiencies of up to $\approx$ $18$ $$ are realised and compared to those predicted by modelling. We highlight the transverse-field slower, which is compact, highly tunable, light-weight, and requires no electrical power, as a simple solution to slowing Sr, well-suited to spaceborne application. For $^{88}$Sr we achieve a slow-atom flux of around $6\times 10^9$ atoms$\,$s$^{-1}$ at $30$ ms$^{-1}$, loading approximately $5\times 10^8$ atoms in to a magneto-optical-trap (MOT), and capture all isotopes in approximate relative natural abundances