Tag-Cloud Drawing: Algorithms for Cloud Visualization

Tag clouds provide an aggregate of tag-usage statistics. They are typically sent as in-line HTML to browsers. However, display mechanisms suited for ordinary text are not ideal for tags, because font sizes may vary widely on a line. As well, the typical layout does not account for relationships that may be known between tags. This paper presents models and algorithms to improve the display of tag clouds that consist of in-line HTML, as well as algorithms that use nested tables to achieve a more general 2-dimensional layout in which tag relationships are considered. The first algorithms leverage prior work in typesetting and rectangle packing, whereas the second group of algorithms leverage prior work in Electronic Design Automation. Experiments show our algorithms can be efficiently implemented and perform well.Comment: To appear in proceedings of Tagging and Metadata for Social Information Organization (WWW 2007

Routing congestion analysis and reduction in deep sub-micron VLSI design

Congestion is one of the main optimization objectives in global routing. However, the optimization performance is constrained because the cells are already fixed at this stage. Therefore, designer can save substantial time and resources by detecting and reducing congested regions during the planning stages. An efficient and yet accurate congestion estimation model is crucial to be included in the inner loop of floorplanning and placement design. In this dissertation, we mainly focus on routing congestion modeling and reduction during floorplanning and placement

Improved Cardinality Bounds for Rectangle Packing Representations

Axis-aligned rectangle packings can be characterized by the set of spatial relations that hold for pairs of rectangles (west, south, east, north). A representation of a packing consists of one satisfied spatial relation for each pair. We call a set of representations complete for n ∈ ℕ if it contains a representation of every packing of any n rectangles. Both in theory and practice, fastest known algorithms for a large class of rectangle packing problems enumerate a complete set R of representations. The running time of these algorithms is dominated by the (exponential) size of R. In this thesis, we improve the best known lower and upper bounds on the minimum cardinality of complete sets of representations. The new upper bound implies theoretically faster algorithms for many rectangle packing problems, for example in chip design, while the new lower bound imposes a limit on the running time that can be achieved by any algorithm following this approach. The proofs of both results are based on pattern-avoiding permutations. Finally, we empirically compute the minimum cardinality of complete sets of representations for small n. Our computations directly suggest two conjectures, connecting well-known Baxter permutations with the set of permutations avoiding an apparently new pattern, which in turn seem to generate complete sets of representations of minimum cardinality

Rectangular Layouts and Contact Graphs

Contact graphs of isothetic rectangles unify many concepts from applications including VLSI and architectural design, computational geometry, and GIS. Minimizing the area of their corresponding {\em rectangular layouts} is a key problem. We study the area-optimization problem and show that it is NP-hard to find a minimum-area rectangular layout of a given contact graph. We present O(n)-time algorithms that construct $O(n^2)$-area rectangular layouts for general contact graphs and $O(n\log n)$-area rectangular layouts for trees. (For trees, this is an $O(\log n)$-approximation algorithm.) We also present an infinite family of graphs (rsp., trees) that require $\Omega(n^2)$ (rsp., $\Omega(n\log n)$) area. We derive these results by presenting a new characterization of graphs that admit rectangular layouts using the related concept of {\em rectangular duals}. A corollary to our results relates the class of graphs that admit rectangular layouts to {\em rectangle of influence drawings}.Comment: 28 pages, 13 figures, 55 references, 1 appendi

Efficient Generation of Rectangulations via Permutation Languages

A generic rectangulation is a partition of a rectangle into finitely many interior-disjoint rectangles, such that no four rectangles meet in a point. In this work we present a versatile algorithmic framework for exhaustively generating a large variety of different classes of generic rectangulations. Our algorithms work under very mild assumptions, and apply to a large number of rectangulation classes known from the literature, such as generic rectangulations, diagonal rectangulations, 1-sided/area-universal, block-aligned rectangulations, and their guillotine variants. They also apply to classes of rectangulations that are characterized by avoiding certain patterns, and in this work we initiate a systematic investigation of pattern avoidance in rectangulations. Our generation algorithms are efficient, in some cases even loopless or constant amortized time, i.e., each new rectangulation is generated in constant time in the worst case or on average, respectively. Moreover, the Gray codes we obtain are cyclic, and sometimes provably optimal, in the sense that they correspond to a Hamilton cycle on the skeleton of an underlying polytope. These results are obtained by encoding rectangulations as permutations, and by applying our recently developed permutation language framework

Bus-driven floorplanning.

Law Hoi Ying.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 101-106).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- VLSI Design Cycle --- p.2Chapter 1.2 --- Physical Design Cycle --- p.6Chapter 1.3 --- Floorplanning --- p.10Chapter 1.3.1 --- Floorplanning Objectives --- p.11Chapter 1.3.2 --- Common Approaches --- p.12Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14Chapter 1.4 --- Motivations and Contributions --- p.15Chapter 1.5 --- Organization of the Thesis --- p.17Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18Chapter 2.1 --- Types of Floorplans --- p.18Chapter 2.2 --- Floorplan Representations --- p.20Chapter 2.2.1 --- Slicing Floorplan --- p.21Chapter 2.2.2 --- Non-slicing Floorplan --- p.22Chapter 2.2.3 --- Mosaic Floorplan --- p.30Chapter 2.3 --- Summary --- p.35Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37Chapter 3.1 --- Introduction --- p.37Chapter 3.2 --- Problem Formulation --- p.38Chapter 3.3 --- Previous Work --- p.38Chapter 3.4 --- Summary --- p.42Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44Chapter 4.1 --- Problem Formulation --- p.44Chapter 4.2 --- Previous Work --- p.45Chapter 4.2.1 --- Abutment Constraint --- p.45Chapter 4.2.2 --- Alignment Constraint --- p.49Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52Chapter 4.3 --- Summary --- p.53Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55Chapter 5.1 --- Introduction --- p.55Chapter 5.2 --- Problem Formulation --- p.56Chapter 5.3 --- Methodology --- p.57Chapter 5.3.1 --- Shape Validation --- p.58Chapter 5.3.2 --- Bus Ordering --- p.65Chapter 5.3.3 --- Floorplan Realization --- p.72Chapter 5.3.4 --- Simulated Annealing --- p.73Chapter 5.3.5 --- Soft Block Adjustment --- p.75Chapter 5.4 --- Experimental Results --- p.75Chapter 5.5 --- Summary --- p.77Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80Chapter 6.1 --- Introduction --- p.80Chapter 6.2 --- Problem Formulation --- p.81Chapter 6.3 --- The Representation --- p.82Chapter 6.3.1 --- Overview --- p.82Chapter 6.3.2 --- Review of TCG --- p.83Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84Chapter 6.3.4 --- Aligning Blocks --- p.85Chapter 6.3.5 --- Solution Perturbation --- p.87Chapter 6.4 --- Simulated Annealing --- p.92Chapter 6.5 --- Soft Block Adjustment --- p.92Chapter 6.6 --- Experimental Results --- p.93Chapter 6.7 --- Summary --- p.94Chapter 6.8 --- Acknowledgement --- p.95Chapter 7 --- Conclusion --- p.99Bibliography --- p.10

A design flow for performance planning : new paradigms for iteration free synthesis

In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing anal ysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is undesirable, and for very high performance designs, infeasible. The problem is likely to become much worse with future generations of technology. To achieve a non-iterative design flow, early synthesis stages should use wire planning to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays

Efficient generation of rectangulations via permutation languages

A generic rectangulation is a partition of a rectangle into finitely many interior-disjoint rectangles, such that no four rectangles meet in a point. In this work we present a versatile algorithmic framework for exhaustively generating a large variety of different classes of generic rectangulations. Our algorithms work under very mild assumptions, and apply to a large number of rectangulation classes known from the literature, such as generic rectangulations, diagonal rectangulations, 1-sided/area-universal, block-aligned rectangulations, and their guillotine variants. They also apply to classes of rectangulations that are characterized by avoiding certain patterns, and in this work we initiate a systematic investigation of pattern avoidance in rectangulations. Our generation algorithms are efficient, in some cases even loopless or constant amortized time, i.e., each new rectangulation is generated in constant time in the worst case or on average, respectively. Moreover, the Gray codes we obtain are cyclic, and sometimes provably optimal, in the sense that they correspond to a Hamilton cycle on the skeleton of an underlying polytope. These results are obtained by encoding rectangulations as permutations, and by applying our recently developed permutation language framework