A low-power reconfigurable ADC for biomedical sensor interfaces

This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC can be tuned to handle a large variety of biopotential signals, with digitally selectable resolution and input signal amplitude. It achieves 10.4-bit of effective resolution sampling at 56kS/s, with a power consumption below 3μW from a 1V voltage supply.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

A simple sub-1V voltage reference

A traditional bandgap reference voltage has a value approximately equal to 1.2V. This is an inconvenient value to obtain in short-channel CMOS circuits where the nominal power supply voltage is 1.2V or lower. Here, a simple circuit is presented to generate a reference voltage between 600mV and 800mV, based on the threshold voltage of a MOS device, which will be suitable for biasing transistors in strong inversion as well as for use in 6-bit data converters needed for high speed data communication systems. The circuit uses a novel, but simple, method for generating the temperature coefficients needed for generating a stable voltage reference across temperature. The core circuit produces a PTAT current that when passed through a diode-connected device, with a CTAT threshold voltage, will produce a voltage that is stable across temperature. The measured results demonstrate an average voltage variation of 4.62mV across five chips, each containing eight voltage reference circuits, and a minimum voltage variation of 1.1mV from 0°C to 80°C. A variation of the proposed circuit replaces the BJTs with MOSFETs to achieve smaller area, and simulation results indicate even less voltage variation across temperature.Electrical and Computer Engineerin

Design of Operational Transconductance Amplifiers for voltage to current conversion in gas sensing applications

This paper presents a study of Operational Transconductance Amplifiers (OTAs) for voltage to current conversion circuits. The paper includes a comparative analysis of three OTA architectures implemented in 0.35\u3bcm CMOS AMS Technology under \ub1 1.65V power supply voltage. The impact of the OTA topology has been investigated by simulation. The designed OTAs managed to deliver large current values of 10mA and 1mA to the load with a worst-case error of 0.02% under worst-case power supply and temperature conditions and a worst percentage error of 0.12% under process variation for both Miller Compensated and Capacitor Multiplier Compensated OTA. \ua9 2016 AEIT

Stray Magnetic Field Compensation with a Scalar Atomic Magnetometer

We describe a system for the compensation of time-dependent stray magnetic fields using a dual channel scalar magnetometer based on non-linear Faraday rotation in synchronously optically pumped Cs vapour. We detail the active control strategy, with an emphasis on the electronic circuitry, based on a simple phase-locked-loop integrated circuit. The performance and limits of the system developed are tested and discussed. The system was applied to significantly improve the detection of free induction decay signals from protons of remotely magnetized water precessing in an ultra-low magnetic field.Comment: 8 pages, 6 figures, 31 refs, v2 (with minor improvements) appearing in Rev.Sc.Instr. June 201

The bias of cosmic voids in the presence of massive neutrinos

Cosmic voids offer an extraordinary opportunity to study the effects of massive neutrinos on cosmological scales. Because they are freely streaming, neutrinos can penetrate the interior of voids more easily than cold dark matter or baryons, which makes their relative contribution to the mass budget in voids much higher than elsewhere in the Universe. In simulations it has recently been shown how various characteristics of voids in the matter distribution are affected by neutrinos, such as their abundance, density profiles, dynamics, and clustering properties. However, the tracers used to identify voids in observations (e.g., galaxies or halos) are affected by neutrinos as well, and isolating the unique neutrino signatures inherent to voids becomes more difficult. In this paper we make use of the DEMNUni suite of simulations to investigate the clustering bias of voids in Fourier space as a function of their core density and compensation. We find a clear dependence on the sum of neutrino masses that remains significant even for void statistics extracted from halos. In particular, we observe that the amplitude of the linear void bias increases with neutrino mass for voids defined in dark matter, whereas this trend gets reversed and slightly attenuated when measuring the relative void-halo bias using voids identified in the halo distribution. Finally, we argue how the original behaviour can be restored when considering observations of the total matter distribution (e.g. via weak lensing), and comment on scale-dependent effects in the void bias that may provide additional information on neutrinos in the future.Comment: 23 pages, 18 figure

A sub-1 V, 26 μw, low-output-impedance CMOS bandgap reference with a low dropout or source follower mode

We present a low-power bandgap reference (BGR), functional from sub-1 V to 5 V supply voltage with either a low dropout (LDO) regulator or source follower (SF) output stage, denoted as the LDO or SF mode, in a 0.5-μm standard digital CMOS process with V tn≈ 0.6 V and |V tp| ≈ 0.7 V at 27 °C. Both modes operate at sub-1 V under zero load with a power consumption of around 26 μW. At 1 V (1.1 V) supply, the LDO (SF) mode provides an output current up to 1.1 mA (0.35 mA), a load regulation of ±8.5 mV/mA (±33 mV/mA) with approximately 10 μ s transient, a line regulation of ±4.2 mV/V (±50μV/V), and a temperature compensated reference voltage of 0.228 V (0.235 V) with a temperature coefficient around 34 ppm/° C from -20°C to 120 °C. At 1.5 V supply, the LDO (SF) mode can further drive up to 9.6 mA (3.2 mA) before the reference voltage falls to 90% of its nominal value. Such low-supply-voltage and high-current-driving BGR in standard digital CMOS processes is highly useful in portable and switching applications. © 2010 IEEE.published_or_final_versio

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability

Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power