A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Analysis And Design Of Wideband Passive Mixer-First Receivers

This dissertation focuses on the design of wideband SAW-less receivers for softwaredefined radios. The entire body of work is based on a single RF front-end architecture type: a passive mixer connected directly to the antenna port of the radio, without an LNA or matching network up front. This structure is inherently wideband which allows for a single receiver front-end to operate at a wide range of frequencies, as tuned by its local oscillator (LO). Additionally, the mixer exhibits the property of transparency from the baseband port of the radio to the RF port of the radio, and vice versa. The focus of the first half of the thesis is on developing a simple theoretical framework for the impedance characteristics of the passive mixer, and implementing a maximally flexible receiver which utilizes the mixer's transparency to the fullest extent. Additionally, it is shown that mixing with 8 non-overlapping phases instead of the traditional 4 has benefits beyond harmonic rejection extending to improved noise performance and increased impedance tuning range. This receiver exhibits low noise figure (~3dB), excellent wideband linearity (IIP3[GREATER-THAN OR EQUAL TO]25dBm), and unprecedented RF impedance control from the baseband side of the passive mixer. Another wideband receiver is presented which explores increasing the number of LO phases even further to 16 and 32, increasing the impedance matching range. The same chip contains a circuit technique for alleviating the shunting effects of LO phase overlap on mixer conversion gain, noise, and impedance match range. Finally in a new design, the power consumption of the receiver architecture is decreased by a factor of 5x (and not scaling with RF frequency). This is done using a resonant LO drive with 8 non-overlapping phases, incorporating the large mixer gate capacitance directly into the LC tank of the VCO. Baseband power consumption is also reduced by reusing current in the four baseband amplifier channels, and performing harmonic rejection, all in one stage of amplification

RF Amplification and Filtering Techniques for Cellular Receivers

The usage of various wireless standards, such as Bluetooth, Wi-Fi, GPS, and 4G/5G cellular, has been continually increasing. In order to utilize the frequency bands efficiently and to support new communication standards with lower power consumption, lower occupied volume and at reduced costs, multimode transceivers, software defined radios (SDRs), cognitive radios, etc., have been actively investigated. Broadband behavior of a wireless receiver is typically defined by its front-end low-noise amplifier (LNA), whose design must consider trade-offs between input matching, noise figure (NF), gain, bandwidth, linearity, and voltage headroom in a given process technology. Moreover, monolithic RF wireless receivers have been trending toward high intermediatefrequency (IF) or superhetrodyne radios thanks to recent breakthroughs in silicon integration of band-pass channel-select filters. The main motivation is to avoid the common issues in the currently predominant zero/low-IF receivers, such as poor 2nd-order nonlinearity, sensitivity to 1/f (i.e. flicker) noise and time-variant dc offsets, especially in the fine CMOS technology. To avoid interferers and blockers at the susceptible image frequencies that the high-IF entails, band-pass filters (BPF) with high quality (Q) factor components for sharp transfer-function transition characteristics are now required. In addition, integrated low-pass filters (LPF) with strong rejection of out-of-band frequency components are essential building blocks in a variety of applications, such as telecommunications, video signal processing, anti-aliasing filtering, etc. Attention is drawn toward structures featuring low noise, small area, high in-/out-of-band linearity performance, and low-power consumption. This thesis comprises three main parts. In the first part (Chapters 2 and 3), we focus on the design and implementation of several innovative wideband low-noise (transconductance) amplifiers [LN(T)A] for wireless cellular applications. In the first design, we introduce new approaches to reduce the noise figure of the noise-cancellation LNAs without sacrificing the power consumption budget, which leads to NF of 2 dB without adding extra power consumption. The proposed LNAs also have the capability to be used in current-mode receivers, especially in discrete-time receivers, as in the form of low noise transconductance amplifier (LNTA). In the second design, two different two-fold noise cancellation approaches are proposed, which not only improve the noise performance of the design, but also achieve high linearity (IIP3=+4.25 dBm). The proposed LN(T)As are implemented in TSMC 28-nm LP CMOS technology to prove that they are suitable for applications such as sub-6 GHz 5G receivers. The second objective of this dissertation research is to invent a novel method of band-pass filtering, which leads to achieving very sharp and selective band-pass filtering with high linearity and low input referred (IRN) noise (Chapter 4). This technique improves the noise and linearity performance without adding extra clock phases. Hence, the duty cycle of the clock phases stays constant, despite the sophisticated improvements. Moreover, due to its sharp filtering, it can filter out high blockers of near channels and can increase the receiver’s blocker tolerance. With the same total capacitor size and clock duty cycle as in a 1st-order complex charge-sharing band-pass filter (CS BPF), the proposed design achieves 20 dB better out-of-band filtering compared to the prior-art 1st-order CS BPF and 10 dB better out-of-band filtering compared to the conventional 2nd-order C-CS BPF. Finally, the stop-band rejection of the discrete-time infinite-impulse response (IIR) lowpass filter is improved by applying a novel technique to enhance the anti-aliasing filtering (Chapter 5). The aim is to introduce a 4th-order charge rotating (CR) discrete-time (DT) LPF, which achieves the record of stop-band rejection of 120 dB by using a novel pseudolinear interpolation technique while keeping the sampling frequency and the capacitor values constant

Energy Efficient Wireless Circuits for IoT in CMOS Technology

The demand for efficient and reliable wireless communication equipment is increasing at a rapid pace. The demand and need vary between different technologies including 5G and IoT. The Radio Frequency Integrated Circuits (RFIC) designers face challenges to achieve higher performance with lower power resources. Although advances in Complementary Metal-Oxide-Semiconductor (CMOS) technology has help designers, challenges still exist. Thus, novel and new ideas are welcome in RFIC design. In this dissertation, many ideas are introduced to improve efficiency and linearity for wireless receivers dedicated to IoT applications. A low-power wireless RF receiver for wireless sensor networks (WSN) is introduced. The receiver has improved linearity with incorporated current-mode circuits and high-selectivity filtering. The receiver operates at a 900 MHz industrial, scientific and medical (ISM) band and is implemented in 130 nm CMOS technology. The receiver has a frequency multiplication mixer, which uses a 300 MHz clock from a local oscillator (LO). The local oscillator is implemented using vertical delay cells to reduce power consumption. The receiver conversion gain is 40 dB and the receiver noise figure (NF) is 14 dB. The receiver IIP3 is −6 dBm and the total power consumption is 1.16 mW. A wireless RF receiver system suitable for Internet-of-Things (IoT) applications is presented. The system can simultaneously harvest energy from out-of-band (OB) blockers with normal receiver operation; thus, the battery life for IoT applications can be extended. The system has only a single antenna for simultaneous RF energy harvesting and wireless reception. The receiver is a mixer-first quadrature receiver designed to tolerate large unavoidable blockers. The system is implemented in 180 nm CMOS technology and operates at 900 MHz industrial, scientific and medical (ISM) band. The receiver gain is 41.5 dB. Operating from a 1 V supply, the receiver core consumes 430 µW. This power can be reduced to 220 µW in the presence of a large blocker (≈ 0 dBm) by the power provided by the blocker RF energy harvesting where the power conversion efficiency (PCE) is 30%. Finally, a highly linear energy efficient wireless receiver is introduced. The receiver architecture is a mixer-first receiver with a Voltage Controlled Oscillator (VCO) based amplifier incorporated as baseband amplifier. The receiver benefits from the high linearity of this amplifier. Moreover, novel clock recycling techniques are applied to make use of the amplifier’s VCOs to clock the mixer circuit and to improve power consumption. The system is implemented in 130 nm CMOS technology and operates at 900 MHz ISM band. The receiver conversion gain is 42 dB and the power consumption is 2.9 mW. The out-of-band IIP3 is 6 dBm. All presented systems and circuits in this dissertation are validated and published in various IEEE journals and conferences

Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog Circuits

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies