Modeling of switched-capacitor delta-sigma Modulators in SIMULINK

Precise behavioral modeling of switched-capacitor /spl Delta//spl Sigma/ modulators is presented. Considering noise (switches' and op-amps' thermal noise), clock jitter, nonidealities of integrators and op-amps including finite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches' clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many /spl Delta//spl Sigma/ modulators' modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a significant underestimation of the modulators' behavior and increase the noise floor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35-/spl mu/m CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

This document is the Accepted Manuscript version of the following article: Junfeng Zhang, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang, and Baoyong Chi, ‘A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver’, IEEE Transactions on Microwave Theory and Practice, Vol. 65 (4): 1303-1314, first published online 16 February 2017. The version of record is available online at DOI: 10.1109/TMTT.2017.266237, Published by IEEE. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A fourth-order quadrature bandpass continuous-time sigma-delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital-analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.Peer reviewe

1-Synchronous Programming of Large Scale, Multi-Periodic Real-Time Applications with Functional Degrees of Freedom

The design and implementation of reactive, hard real-time systems involves modeling and generating efficient code for the integration of harmonic multi-periodic tasks. Such a reactive system can be modeled as a synchronous program orchestrating computations, state machine transitions and communications. In a harmonic multi-periodic integration program, task execution rates are related through integral ratios. This paper aims at providing a scalable way to implement large systems composed of modular, synchronous reactive tasks, and to generate efficient code satisfying real-time constraints.The paper describes three incremental extensions to the Lustre language and evaluates them on production applications. First, we propose a clock calculus for 1-synchronous clocks, i.e. strictly periodic clocks with a single activation on their period; we show how the compiler can exploit this information to raise the level of abstraction when integrating tasks at the system level. Second, we allow some variables to have unknown phases, extending the clock inference to gather constraints on unknown phases, using a solver for load balancing over multi-periodic real-time schedules, before instantiating this solution to assign clocks to all reactions of the system. Third, we propose temporally underspecified operations, relevant to many discrete control scenarii, for example on variables with low temporal variability; we show how to express this in a composable way, retaining the Kahn semantics of the synchronous program outside these controlled relaxations, and exploiting slack in the computation to relax the constraints of the real-time load-balancing problem

Systems Design of Correction Coding

Nejen při přenosu dat díky zvyšování přenosové rychlosti se lze stále častěji setkat s chybami, které mají tendenci shlukovat se. Hledání alternativních řešení korekce shlukových chyb k dosud používaným metodám je v oblasti zájmu předkládané práce. Cílem je detailně rozebrat problematiku konvolučních kódů pro opravu shluku chyb, jenž mohou být využitelné v individuálních protichybových systémech a dosáhnout tak lepších výsledků než při hromadné aplikaci stávajících řešení. Nejprve jsou stručně popsány stávající využívané metody k odstranění či potlačení shlukových chyb. Následuje část věnovaná jednotlivým systematickým konvolučním kódům, kde jsou dané kódy podrobně popsány rozsáhlým matematickým aparátem, jenž rozšiřuje soubor možných hodnotících kritérií protichybových systémů, které jdou uplatnit při posuzování návrhu individuálních řešení. Získané vlastnosti kódů jsou konfrontovány jak mezi konvolučními kódy tak i s dalšími variantami návrhů ochrany zprávy před shlukem chyb. Pro prověření správnosti odvozeného matematického aparátu jsou zpracované konvoluční kódy podrobeny kontrole pomocí simulací v Matlabu. Jelikož simulace představuje základní používanou metodu pro ověření i prezentování již navrženého zabezpečovacího procesu a umožňuje lepší pohled na danou problematiku. Realizovatelnost individuálních protichybových systémů je následně ověřována pomocí vytváření popisu chování obvodu jazykem VHDL. Jeho velká přenositelnost, představuje podstatnou výhodu při návrhu individuálních systémů vlastní realizace.Due to growing transmission speed burst-forming errors tend to occur still more frequently not exclusively in data transmission. The presented paper concentrates on the search for alternative burst error correction solutions complementing the existing methods in use. Its objective is an elaboration of a detailed analysis of the issue of convolution codes for error burst correction which can be used in individual anti-error systems and thus an achievement of better results than those attained by mass application of the existing solutions. First the methods implemented to remove or suppress burst errors are briefly characterized. This part is followed by a detailed description of the individual systematic convolution codes by means of mathematical tools which extend the set of possible evaluative criteria of anti-error systems which can be applied while assessing proposals for individual solutions. The acquired code properties are compared with convolution codes as well as with other versions of proposals for message protection against an error burst. The processed convolution codes are subject to testing by means of Matlab mathematical programme simulation in order to validate the correctness of the derived mathematical tools. This is because simulation represents the principal method applied to verify and present an already proposed security process and enables the acquisition of a better overview of the issue at hand. The feasibility of the individual anti-error systems is then confirmed by way of creating a circuit behaviour description in the VHDL language. Its high portability presents a big advantage when drafting individual systems of the actual implementation.

Fuel cell and supercapacitors remote control car

The energetic crisis and the actual fossil fuel dependant society make an alternative energy sources necessary. In a world where pollution is massively emitted and consumption has no end a cleaner energy source is needed. The hydrogen is a very good option because its use is very clean and is the more common element in the universe and also abundant in the earth. Nevertheless the hydrogen also has some disadvantages like high flammability, expensive obtaining and difficult storage. To solve or decrease these disadvantages the hydrogen must work with other energy sources like supercapacitors. If newer technologies are developed, more investigation will be done and the hydrogen problems will be solved with time. In this report of a 5 month project all the technological aspects involved in the conception and creation of a hydrogen car are explained. The purpose of this project is to make an approach of a real and nowadays car industry problem: Energy management of an electric hybrid car. The car in this project is five times smaller and its power needs are lower too, but the problem in managing the different power supplying sources remains. In this actual project the power supply sources are a 300 W fuel cell and a 29 F supercapacitor. To make an accurate approach to the real problem the real requirements are tried to be accomplished: - Same acceleration as Porsche 911GT: The speed reached by a remote control car won’t be the same as the real car, but the acceleration of the car can be the same but in a lower speed. The Porsche 911GT reaches 100 km/h in 4,2 seconds (a = 6,614 m/s2), so this car would do the same if it could reach 100 km/h. - Brake: The brake system is an essential system for any car and must guarantee a rapid stop of the car. - Reverse gear: This is important to park a car and do some maneuvers occasionally. Some of these requirements are essentials and others are not and there are also very difficult requirements and easier requirements. All of them are kept in mind while doing this research project.Outgoin

Polyhedral Scheduling and Relaxation of Synchronous Reactive Systems

International audienceThe design and implementation of reactive, hard real-time systems involves modeling and generating efficient code for the integration of harmonic multi-periodic tasks. The simple principles of synchronous reactive programming met great scientific and engineering success in the area. A synchronous program orchestrates concurrent computations. It does so while maintaining composability, modularity, functional determinism and real-time execution guarantees. In the case of hard real-time systems, a reactive control program is composed of multi-periodic tasks related through integral ratios. This paper presents a language and optimizing compiler to implement large reactive control systems composed of multi-periodic, synchronous reactive tasks. The same language is used to program a complete control system, from the finest-grained computations to task-level integration, while generating efficient code satisfying real-time constraints. It is evaluated on two real-world applications

Smart Biomechanical Adaptation Revealed by the Structure of Ostrich Limb Bones

Ostriches are known to be the fastest bipedal animal alive; to accomplish such an achievement, their anatomy evolved to sustain the stresses imposed by running at such velocities. Ostriches represent an excellent case study due to the fact that their locomotor kinematics have been extensively studied for their running capabilities. The shape and structure of ostrich bones are also known to be optimized to sustain the stresses imposed by the body mass and accelerations to which the bones are subjected during movements. This study focuses on the limb bones, investigating the structure of the bones as well as the material properties, and how both the structure and material evolved to maximise the performance while minimising the stresses applied to the bones themselves. The femoral shaft is hollowed and it presents an imbricate structure of fused bone ridges connected to the walls of the marrow cavity, while the tibial shaft is subdivided into regions having different mechanical characteristics. These adaptations indicate the optimization of both the structure and the material to bear the stresses. The regionalization of the material highlighted by the mechanical tests represents the capability of the bone to adapt to external stimuli during the life of an individual, optimizing not only the structure of the bone but the material itself

Conception d'un convertisseur PUC5 dans un système multicellulaire et multiniveau de basse tension

De nos jours, les convertisseurs multiniveaux et modulaires (MMC) sont devenus un des principaux sujets de recherche en électronique de puissance pour plusieurs raisons : faible THD, possibilité de moyennes et hautes tensions, modularité, etc. Or, ils s’adaptent bien mal aux applications de faible tension qui, eux aussi, bénéficieraient de ces avantages. Conséquemment, l’utilisation de cette topologie série engendrerait des cellules dont la tension est très faible, ce qui n’est pas pratique. Une topologie parallèle a été développée qui permet de garder la stratégie modulaire du MMC pour les applications de faible tension. Un onduleur de 5 niveaux de type « Packed U-Cell » (PUC5) a été utilisé pour implémenter l’algorithme. De plus, des transistors au Nitrure de Gallium (GaN) ont été utilisés. Des formes d’onde multiniveaux sont générées au point de couplage commun (PCC) CA à l’aide d’une inductance interbranche et d’un déphasage entre les porteuses triangulaires des cellules. Le contrôle de cette topologie est décentralisé, c’est-à-dire que chaque convertisseur n’a besoin que des paramètres du réseau électrique et d’un pulse de synchronisation. Les résultats de simulation et d’expérimentation sont présentés pour un système autonome et monophasé