Modulation Scheme Analysis for Low-Power Leadless Pacemaker Synchronization Based on Conductive Intracardiac Communication

Conductive intracardiac communication (CIC) has been demonstrated as a promising concept for the synchronization of multi-chamber leadless cardiac pacemakers (LLPMs). To meet the 2–5 μ W power budget of a LLPM, highly specialized CIC-transceivers, which make optimal use of the cardiac communication channel, need to be developed. However, a detailed investigation of the optimal communication parameters for CIC-based LLPM synchronization is missing so far. This work analyzes the intracardiac communication performance of two low-power modulation techniques, namely On-Off-Keying (OOK) and Manchester-encoded baseband transmission (BB-MAN), as a function of the transmitted bit-energy. The bit error rate (BER) of a prototype dual-chamber LLPM was determined both in simulation and in-vitro experiments on porcine hearts. A BER of 1e − 4 was achieved with a median bit-energy in the range of 3-16 pJ (interquartile range: 4-15 pJ) for data rates from 75-500 kbps and a receiver input noise density of 7 nV/ √Hz . Both modulation schemes showed comparable performance, with BB-MAN having a slight bit-energy advantage (1-2 dB at 150-500 kbps) under equalized transceiver characteristics. This study demonstrates that reliable CIC-based LLPM synchronization is feasible at transmitted power levels < 10 nW under realistic channel conditions and receiver noise performance. Therefore, modulation techniques such, as BB-MAN or OOK, are preferable over recently proposed alternatives, such as pulse position modulation or conductive impulse signaling, since they can be realized with fewer hardware resources and smaller bandwidth requirements. Ultimately, a baseband communication approach might be favored over OOK, due to the more efficient cardiac signal transmission and reduced transceiver complexity

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers

LOW-POWER IMPULSE-RADIO ULTRA-WIDEBAND TECHNIQUES FOR BIOMEDICAL APPLICATIONS.

Ph.DDOCTOR OF PHILOSOPH

Inductively Coupled CMOS Power Receiver For Embedded Microsensors

Inductively coupled power transfer can extend the lifetime of embedded microsensors that save costs, energy, and lives. To expand the microsensors' functionality, the transferred power needs to be maximized. Plus, the power receiver needs to handle wide coupling variations in real applications. Therefore, the objective of this research is to design a power receiver that outputs the highest power for the widest coupling range. This research proposes a switched resonant half-bridge power stage that adjusts both energy transfer frequency and duration so the output power is maximally high. A maximum power point (MPP) theory is also developed to predict the optimal settings of the power stage with 98.6% accuracy. Finally, this research addresses the system integration challenges such as synchronization and over-voltage protection. The fabricated self-synchronized prototype outputs up to 89% of the available power across 0.067%~7.9% coupling range. The output power (in percentage of available power) and coupling range are 1.3× and 13× higher than the comparable state of the arts.Ph.D

Resource Allocation Challenges and Strategies for RF-Energy Harvesting Networks Supporting QoS

This paper specifically addresses the resource allocation challenges encountered in wireless sensor networks that incorporate RF energy harvesting capabilities, commonly referred to as RF-energy harvesting networks (RF-EHNs). RF energy harvesting and transmission techniques bring substantial advantages for applications requiring Quality of Service (QoS) support, as they enable proactive replenishment of&nbsp; wireless devices. We commence by providing an overview of RF-EHNs, followed by an in-depth examination of the resource allocation challenges associated with this technology. In addition, we present a case study that focuses on the design of an efficient operating strategy for RF-EHN receivers. Our investigation highlights the critical aspects of service differentiation and QoS support, which have received limited attention in previous research. Besides, we explore previously unexplored areas within these domains

A 3.1-4.8GHz IR-UWB All-Digital Pulse Generator in 0.13-um CMOS Technology for WBAN Systems

Analog, Digital & RF Circuit DesignImpulse Radio Ultra-WideBand (IR-UWB) systems have drawn growing attention for wireless sensor networks such as Wireless Personal Area Network (WPAN) and Wireless Body Area Network (WBAN) systems ever since the Federal Communications Commission (FCC) released the spectrum between 3.1 and 10.6GHz for unlicensed use in 2002. The restriction on transmitted power spectral density in this band is equal to the noise emission limit of household digital electronics. This band is also shared with several existing service, therefore in-band interference is expected and presents a challenge to UWB system design. UWB devices as secondary spectrum users must also detect and avoid (DAA) other licensed users from the cognitive radio???s point of view. For the DAA requirement, it is more effective to deploy signal with variable center frequency and a minimum 10dB bandwidth of 500MHz than a signal covering the entire UWB spectrum range with fixed center frequency. A key requirement of the applications using IR-UWB signal is ultra-low power consumption for longer battery life. Also, cost reduction is highly desirable. Recently, digital IR-UWB pulse generation is studied more than analog approach due to its lower power consumption. An all-digital pulse generator in a standard 0.13-um CMOS technology for communication systems using Impulse Radio Ultra-WideBand (IR-UWB) signal is presented. A delay line-based architecture utilizing only static logic gates and leading lower power consumption for pulse generation is proposed in this thesis. By using of all-digital architecture, energy is consumed by CV2 switching losses and sub-threshold leakage currents, without RF oscillator or analog bias currents. The center frequency and the fixed bandwidth of 500MHz of the output signal can be digitally controlled to cover three channels in low band of UWB spectrum. Delay based Binary Shift Keying (DB-BPSK) and Pulse Position Modulation (PPM) schemes are exploited at the same time to modulate the transmitted signals with further improvement in spectrum characteristics. The total energy consumption is 48pJ/pulse at 1.2V supply voltage, which is well suitable for WBAN systems.ope

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

A nonlinear dynamic system for spread spectrum code acquisition

Thesis (S.M.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 1999.Includes bibliographical references (leaves 88-89).Nonlinear differential equations and iterated maps can perform any computation. Sometimes, the most difficult part of performing a useful computation, however, is writing the program. Furthermore, in practice, we often need to build special purpose computing hardware suited to run a particular program. Nonlinear dynamics provides a novel and useful language for constructing "algorithms" and "computer architectures." We apply the language of nonlinear dynamics to solve a fast coding problem which has previously been implemented by a Digital Signal Processor chip in digital wireless receivers. We eventually hope to produce a novel physical system which exhibits the nonlinear dynamics we require, thereby creating one of the first nonlinear dynamic systems engineered to perform a practical computation. This system, called an Analog Feedback Shift Register (AFSR), should be a faster, more reliable, less expensive, and lower power Spread Spectrum (SS) code acquisition system for wireless receivers. A prohibitive factor in creating ubiquitous short range, digital radio transceivers is the difficulty and expense of creating a mechanism for locking onto the incoming Spread Spectrum code sequence. AFSR is also potentially useful in other applications where low cost, low power channel sharing or addressing is required, for example in wireless auto-identification tags.by Benjamin William Vigoda.S.M