Digital controlled oscillator (DCO) for all digital phase-locked loop (ADPLL) – a review

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL

Low power digitally controlled oscillator for IoT applications

This work is focused on the design of a Low Power CMOS DCO for IEEE 802.11ah in IoT applications. The design methodology is based on the Unified current-control model (UICM), which is a physics-based model and enables an accurate all-region model of the operation of the device. Additionally, a transformer-based resonator has been used to solve the low-quality factor issue of integrated inductors. Two digitally controlled oscillators (DCO) have been implemented to show the advantages of utilizing a transformedbased resonator and the methodology based on the UICM model. These designs aim for the operation in low voltage supply (VDD) since VDD scaling is a trend in systems-onchip (SoCs), in which the circuitry is mostly digital. Despite the degradation caused by VDD scaling, new RF and analog circuits must deliver similar performance of the older CMOS nodes. The first DCO design was a low power LC-tank DCO, implemented in 40nm bulk-CMOS. The first design presented a DCO operating at 45% of the nominal VDD without compromise the performance. By reducing the VDD below the nominal value, this DCO reduces power consumption, which is a crucial feature for IoT circuits. The main contribution of this first DCO is the reduction of VDD scaling impact on the phase-noise do the DCO. The LC-based DCO operates from 1.8 to 1.86 GHz. At the maximum frequency and 0.395V VDD, the power consumption is a mere 380 W with a phase-noise of -119.3 dBc/Hz at 1 MHz. The circuit occupies an area of 0.46mm2 in 40 nm CMOS, mostly due to the inductor. The second DCO design was a low-power transformer-based DCO design, implemented in 28nm bulk-CMOS. This second design aims for the VDD reduction to below 0.3 V. Operating in a frequency range similar to the LC-based DCO, the transformer-based DCO operated with 0.280V VDD with a power consumption of 97 W. Meanwhile, the phase-noise was -101.95 dBc/Hz at 1 MHz. Even in the worst-case scenario (i.e., slow-slow and 85oC), this second DCO was able to operate at 0.330V VDD, consuming 126 W, while it keeps a similar phase-noise performance of the typical case. The core circuit occupies an area of 0.364 mm2.Este trabalho objetiva o projeto de um DCO de baixa potência em CMOS para aplicações de IoT e aderentes ao padrão IEEE 802.11ah. A metodologia de projeto é baseada no modelo de controle de corrente unificado (UICM), que é um modelo com embasamento físico que permite uma operação precisa em todas as regiões de operação do dispositivo. Adicionalmente, é utilizado um ressonador baseado em transformador visando solucionar os problemas provenientes do baixo fator de qualidade de indutores integrados. Para destacar as melhorias obtidas com o projeto do ressonador baseado em transformador e com a metodologia baseada no modelo UICM, dois projetos de DCO são realizados. Esses projetos visam a operação com baixa tensão de alimentação (VDD), uma vez que o escalonamento do VDD é uma tendência em sistemas em chip (SoCs), em que o circuito é majoritariamente digital. Independente da degradação causada pelo escalonamento de VDD, circuitos analógicos e de RF atuais devem oferecer desempenho semelhante ao alcançado em tecnologias CMOS mais antigas. O primeiro projeto foi um DCO de baixa potência com tanque LC, implementado em tecnologia bulk-CMOS de 40nm. O primeiro projeto apresentou uma operação a 45% do VDD nominal sem comprometer o desempenho. Ao reduzir o VDD abaixo do valor nominal, este DCO reduz o consumo de energia, que é uma característica crucial para circuitos IoT. A principal contribuição deste DCO é a redução do impacto do escalonamento do VDD no ruído de fase. O DCO com tanque LC opera de 1,8 a 1,86 GHz. Na frequência máxima e com VDD de apenas 0,395V, o consumo de energia é 380 W e o ruído de fase é -119,3 dBc/Hz a 1 MHz. O circuito ocupa uma área de 0.46mm2 em processo CMOS de 40 nm. O segundo projeto foi um DCO de baixa potência baseado em transformador, implementado em tecnologia bulk- CMOS de 28nm. Este projeto visa a redução de VDD abaixo de 0,3 V. Operando em uma faixa de frequência semelhante ao primeiro DCO, o DCO baseado em transformador opera com VDD de 0,280V e com consumo de potência de 97 W. O ruído de fase foi de -101,95 dBc/Hz a 1 MHz. Mesmo no pior caso de processo, este DCO opera a um VDD de 0,330V, consumindo 126 W, com o ruído de fase semelhante ao caso típico. O circuito ocupa uma área de 0.364mm2

Millimeter-Wave CMOS Digitally Controlled Oscillators for Automotive Radars

All-Digital-Phase-Locked-Loops (ADPLLs) are ideal for integrated circuit implementations and effectively generate frequency chirps for Frequency-Modulated-Continuous-Wave (FMCW) radar. This dissertation discusses the design requirements for integrated ADPLL, which is used as chirp synthesizer for FMCW automotive radar and focuses on an analysis of the ADPLL performance based on the Digitally-Controlled-Oscillator (DCO) design parameters and the ADPLL configuration. The fundamental principles of the FMCW radar are reviewed and the importance of linear DCO for reliable operation of the synthesizer is discussed. A novel DCO, which achieves linear frequency tuning steps is designed by arranging the available minimum Metal-Oxide-Metal (MoM) capacitor in unique confconfigurations. The DCO prototype fabricated in 65 nm CMOS fullls the requirements of the 77 GHz automotive radar. The resultant linear DCO characterization can effectively drive a chirp generation system in complete FMCW automotive radar synthesizer

Microwave Spectroscopy of a Cooper-Pair Transistor Coupled to a Lumped-Element Resonator

We have studied the microwave response of a single Cooper-pair transistor (CPT) coupled to a lumped-element microwave resonator. The resonance frequency of this circuit, $f_{r}$, was measured as a function of the charge $n_{g}$ induced on the CPT island by the gate electrode, and the phase difference across the CPT, $\phi_{B}$, which was controlled by the magnetic flux in the superconducting loop containing the CPT. The observed $f_{r}(n_{g},\phi_{B})$ dependences reflect the variations of the CPT Josephson inductance with $n_{g}$ and $\phi_{B}$ as well as the CPT excitation when the microwaves induce transitions between different quantum states of the CPT. The results are in excellent agreement with our simulations based on the numerical diagonalization of the circuit Hamiltonian. This agreement over the whole range of $n_{g}$ and $\phi_{B}$ is unexpected, because the relevant energies vary widely, from 0.1K to 3K. The observed strong dependence $f_{r}(n_{g},\phi_{B})$ near the resonance excitation of the CPT provides a tool for sensitive charge measurements.Comment: 10 pages, 6 figure

Evolution of digitally controlled oscillator

Suvremeni razvoj uporabe digitalnih ili potpuno digitalnih ciklusa s faznim podešavanjem (PLLs) u različitim uređajima za komunikaciju vodi ka primjeni digitalno kontroliranog oscilatora (DCO). U ovom se preglednom članku daje razvoj DCO-a u modernim elektroničkim uređajima kao i njihovo funkcioniranje u lokalnim oscilatorima. Iako se implementacija DCO preferira u odnosu na analogne, i dalje se radi na poboljšanjima u potrošnji energije, brzini, veličini čipa, raspona frekvencije, ulaznog napona, prenosivosti i rezolucije. U radu se uglavnom opisuje razvoj od oscilatora kontroliranih voltažom (voltage controlled oscillators- VCO) do digitalno kontroliranih oscilatora za "deep-submicrometer CMOS" postupak. Fokus je na analizi i praćenju unapređenja DCO-a na razini funkcionalnosti.Current trend of using digital or all-digital phase-locked loops (PLLs) in various communication devices introduces the usage of digitally controlled oscillator (DCO). This review paper discusses the evolution of DCOs in modern electronic devices as well as their performances in local oscillators. Even though the DCO implementation is preferable to its analog counterpart, improvements are still going on to get high performances in terms of power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. This paper mainly describes the evolution of DCO, how it turns from a conventional VCO to DCO for deep-submicrometer CMOS process. The focus is to analyse and track the advances in DCO base on its performance level

A Single-Trim frequency reference system with 0.7 ppm/°C from −63 °C to 165 °C Consuming 210 μW at 70 MHz

This article presents a frequency reference system that combines high frequency accuracy and low power consumption using a single-point temperature trim and batch calibration. The system is intended as a low-cost fully integrated crystal oscillator replacement. In this system, the oscillation frequency of a power-efficient, but process, voltage, temperature (PVT) and lifetime (L)-sensitive current-controlled ring oscillator (CCO) is periodically (re)calibrated by the well-behaved frequency stability of an untuned LC -based Colpitts oscillator (LCO), which is optimized for stability over PVT variations and lifetime (PVTL). During the single-point room temperature factory trim, the frequency of the LCO is determined and the result is digitally stored. An on-chip calibration engine tunes the CCO to the target frequency based on the LCO frequency, temperature sensor information, and digitally stored trimming information, thus effectively improving the frequency stability of the ring oscillator. The relatively high-power LCO is heavily duty-cycled to minimize the overall power consumption. A prototype fabricated in a 0.13- μ m high-voltage (HV) CMOS SOI process and assembled in a plastic package demonstrates an inaccuracy lower than ±93 ppm over a temperature range from -63 °C to 165 °C across 18 samples. The presented frequency reference system, including on-chip voltage regulators and a temperature sensor, occupies a chip area of 0.69 mm2 and consumes about 64 μA from a single 3.3-V supply. The frequency error due to supply variation is roughly 92 ppm/V. The mean frequency shift due to aging, measured before and after a six-day storage bake at 175 °C, is only 52 ppm.</p

Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones

Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits and data converters based on frequency-encoding. This research has been motivated by the needs of consumer electronics industry, which constantly demands more compact readout circuit for MEMS microphones and other sensors. Nowadays, data acquisition is mainly based on encoding signals in voltage or current domains, which is becoming more challenging in modern deep submicron CMOS technologies. Frequency-encoding is an emerging signal processing technique based on encoding signals in the frequency domain. The key advantage of this approach is that systems can be implemented using mostly-digital circuitry, which benefits from CMOS technology scaling. Frequencyencoding can be used to build phase referenced integrators, which can replace classical integrators (such as switched-capacitor based integrators) in the implementation of efficient analog-to-digital converters and sensor interfaces. The core of the phase referenced integrators studied in this thesis consists of the combination of different oscillator topologies with counters and highly-digital circuitry. This work addresses two related problems: the development of capacitive MEMS sensor readout circuits based on frequency-encoding, and the design and implementation of compact oscillator-based data converters for audio applications. In the first problem, the target is the integration of the MEMS sensor into an oscillator circuit, making the oscillation frequency dependent on the sensor capacitance. This way, the sound can be digitized by measuring the oscillation frequency, using digital circuitry. However, a MEMS microphone is a complex structure on which several parasitic effects can influence the operation of the oscillator. This work presents a feasibility analysis of the integration of a MEMS microphone into different oscillator topologies. The conclusion of this study is that the parasitics of the MEMS limit the performance of the microphone, making it inefficient. In contrast, replacing conventional ADCs with frequency-encoding based ADCs has proven a very efficient solution, which motivates the next problem. In the second problem, the focus is on the development of high-order oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical integrators and phase referenced integrators has been studied, followed by an overview of state-of-art oscillator-based converters. Then, a procedure to replace classical integrators by phase referenced integrators is presented, including a design example of a second-order oscillator based Sigma-Delta modulator. Subsequently, the main circuit impairments that limit the performance of this kind of implementations, such as phase noise, jitter or metastability, are described. This thesis also presents a methodology to evaluate the impact of phase noise and distortion in oscillator-based systems. The proposed method is based on periodic steady-state analysis, which allows the rapid estimation of the system dynamic range without resorting to transient simulations. In addition, a novel technique to analyze the impact of clock jitter in Sigma-Delta modulators is described. Two integrated circuits have been implemented in 0.13 μm CMOS technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder noise shaping using only oscillators and digital circuitry. The first testchip shows a malfunction in the digital circuitry due to the complexity of the multi-bit counters. The second chip, implemented using single-bit counters for simplicity, shows second-order noise shaping and reaches 103 dB-A of dynamic range in the audio bandwidth, occupying only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces para sensores capacitivos basados en codificación en frecuencia. Esta investigación está motivada por las necesidades de la industria, que constantemente demanda reducir el tamaño de este tipo de circuitos. Hoy en día, la adquisición de datos está basada principalmente en la codificación de señales en tensión o en corriente. Sin embargo, la implementación de este tipo de soluciones en tecnologías CMOS nanométricas presenta varias dificultades. La codificación de frecuencia es una técnica emergente en el procesado de señales basada en codificar señales en el dominio de la frecuencia. La principal ventaja de esta alternativa es que los sistemas pueden implementarse usando circuitos mayoritariamente digitales, los cuales se benefician de los avances de la tecnología CMOS. La codificación en frecuencia puede emplearse para construir integradores referidos a la fase, que pueden reemplazar a los integradores clásicos (como los basados en capacidades conmutadas) en la implementación de conversores analógico-digital e interfaces de sensores. Los integradores referidos a la fase estudiados en esta tesis consisten en la combinación de diferentes topologías de osciladores con contadores y circuitos principalmente digitales. Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos de lectura para sensores MEMS capacitivos basados en codificación temporal, y el diseño e implementación de conversores de datos compactos para aplicaciones de audio basados en osciladores. En el primer caso, el objetivo es la integración de un sensor MEMS en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos en su mayor parte digitales. Sin embargo, un micrófono MEMS es una estructura compleja en la que múltiples efectos parasíticos pueden alterar el correcto funcionamiento del oscilador. Este trabajo presenta un análisis de la viabilidad de integrar un micrófono MEMS en diferentes topologías de oscilador. La conclusión de este estudio es que los parasíticos del MEMS limitan el rendimiento del micrófono, causando que esta solución no sea eficiente. En cambio, la implementación de conversores analógico-digitales basados en codificación en frecuencia ha demostrado ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente problema. La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado la equivalencia entre los integradores clásicos y los integradores referidos a la fase, seguido de una descripción de los conversores basados en osciladores publicados en los últimos años. A continuación se presenta un procedimiento para reemplazar integradores clásicos por integradores referidos a la fase, incluyendo un ejemplo de diseño de un modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente se describen los principales problemas que limitan el rendimiento de este tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad. Esta tesis también presenta un nuevo método para evaluar el impacto del ruido de fase y de la distorsión en sistemas basados en osciladores. El método propuesto está basado en simulaciones PSS, las cuales permiten la rápida estimación del rango dinámico del sistema sin necesidad de recurrir a simulaciones temporales. Además, este trabajo describe una nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta. En esta tesis se han implementado dos circuitos integrados en tecnología CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han sido diseñados para producir conformación espectral de ruido de segundo orden, usando únicamente osciladores y circuitos mayoritariamente digitales. El primer chip ha mostrado un error en el funcionamiento de los circuitos digitales debido a la complejidad de las estructuras multi-bit utilizadas. El segundo chip, implementado usando contadores de un solo bit con el fin de simplificar el sistema, consigue conformación espectral de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus

Monitor-Based In-Field Wearout Mitigation for CMOS RF Integrated Circuits

abstract: Performance failure due to aging is an increasing concern for RF circuits. While most aging studies are focused on the concept of mean-time-to-failure, for analog circuits, aging results in continuous degradation in performance before it causes catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on the devices. In this dissertation, firstly, a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices at design-time (pre-silicon) is presented. An algorithm to determine reliability hotspots in the circuit is proposed and design-time optimization methods to enhance the lifetime by making the most likely to fail circuit components more reliable is performed. RF circuits are used as test cases to demonstrate that the lifetime can be enhanced using the proposed design-time technique with low area and no performance impact. Secondly, in-field monitoring and recovering technique for the performance of aged RF circuits is discussed. The proposed in-field technique is based on two phases: During the design time, degradation profiles of the aged circuit are obtained through simulations. From these profiles, hotspot identification of aged RF circuits are conducted and the circuit variable that is easy to measure but highly correlated to the performance of the primary circuit is determined for a monitoring purpose. After deployment, an on-chip DC monitor is periodically activated and its results are used to monitor, and if necessary, recover the circuit performances degraded by aging mechanisms. It is also necessary to co-design the monitoring and recovery mechanism along with the primary circuit for minimal performance impact. A low noise amplifier (LNA) and LC-tank oscillators are fabricated for case studies to demonstrate that the lifetime can be enhanced using the proposed monitoring and recovery techniques in the field. Experimental results with fabricated LNA/oscillator chips show the performance degradation from the accelerated stress conditions and this loss can be recovered by the proposed mitigation scheme.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application

All Digital Phase Locked Loop (ADPLL) has many applications in digital communication. It is difficult for low-frequency applications to achieve the lock state quickly. Therefore, proposed a novel particle swarm based ADPLL (PS-ADPLL) with Coordinate Rotation Digital Computer (CORDIC) algorithm to attain the lock state of the ADPLL for the low-frequency applications. In the proposed architecture, the D flip-flop matches the frequency and the phase of the output and reference pulses and produces an error signals up and down signal. The up/down counter removes the higher frequency part and produces a carry and the borrow signal. These carry and borrow signals are then fed into the increment decrement counters to produce the output signal matching the frequency of the reference signal. However, the time delay is increased for low-frequency applications, which is critical for the lock state. So, the delay line length is calculated by the CORDIC algorithm and is optimized by the particle swarm activated in the phase detector to match the output pulse with the reference pulse and make ADPLL into a locked state. The presented PS-ADPLL is tested in FPGA. Furthermore, the performance parameters are evaluated and compared with other current techniques to calculate the improvement score